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UPD70F3201 の電気的特性と機能

UPD70F3201のメーカーはNECです、この部品の機能は「32-BIT SINGLE-CHIP MICROCONTROLLERS」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD70F3201
部品説明 32-BIT SINGLE-CHIP MICROCONTROLLERS
メーカ NEC
ロゴ NEC ロゴ 




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UPD70F3201 Datasheet, UPD70F3201 PDF,ピン配置, 機能
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD703201,
703201Y,
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703204, 703204Y,
70F3201, 70F3201Y, 70F3204, 70F3204Y
V850ES/SA2TM, V850ES/SA3TM
32-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703201, 703201Y, 70F3201, and 70F3201Y (V850ES/SA2), µPD703204, 703204Y, 70F3204, and
70F3204Y (V850ES/SA3) are products in the V850 FamilyTM of 32-bit single-chip microcontrollers, and include
peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a
DMA controller.
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/SA2
and V850ES/SA3 include instructions suited to digital servo control applications such as multiplication instructions
executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. As a real-time control
system, this device provides a high-level cost performance ideal for ultra-low-power DVC and portable audio
applications.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850ES/SA2, V850ES/SA3 User’s Manual Hardware:
To be prepared
V850ES User’s Manual Architecture:
To be prepared
FEATURES
{ Number of instructions: 83
{ Interrupts and exceptions
{ Minimum instruction execution time:
Non-maskable interrupts: 2 sources
59 ns (@ 17 MHz operation with main system clock (fXX))
Maskable interrupts:
74 ns (@ 13.5 MHz operation with main system clock (fXX))
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
38 sources (µPD703201, 70F3201)
39 sources (µPD703201Y, 70F3201Y)
39 sources (µPD703204, 70F3204)
Signed multiplication, saturation operations, 32-bit
40 sources (µPD703204Y, 70F3204Y)
shift instructions, bit manipulation instructions,
Software exceptions: 32 sources
load/store instructions
Exception trap: 1 source
{ Memory space:
{ I/O lines Total: 82 (V850ES/SA2)
64 MB linear address space
102 (V850ES/SA3)
Memory block division function:
{ Timer/counters
2 MB, 2 MB, 4 MB, 8 MB = Total four blocks
16-bit timer: 2 channels
{ External bus interface: 16-bit data bus
8-bit timer: 4 channels
Address bus: Separate output enabled
{ Internal memory
{ Real-time counter (for watch): 1 channel
{ Watchdog timer: 1 channel
Mask ROM: 256 KB (µPD703201, 703201Y,
703204, 703204Y)
Flash memory: 256 KB (µPD70F3201, 70F3201Y,
70F3204, 70F3204Y)
RAM: 16 KB
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15436EJ1V0PM00 (1st edition)
Date Published June 2001 N CP(K)
Printed in Japan
©
2001

1 Page





UPD70F3201 pdf, ピン配列
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
PIN CONFIGURATION
V850ES/SA2
100-pin plastic LQFP (fine-pitch) (14 × 14)
µPD703201GC-×××-8EU
µPD703201YGC-×××-8EU
µPD70F3201GC-8EU
µPD70F3201YGC-8EU
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AVREF0
AVDD
AVSS
P80/ANO0
P81/ANO1
AVREF1
P00/NMI
P30/SI1/RXD0
P31/SO1/TXD0
P32/SCK1
VDD
VSS
X1
X2
RESET
XT1
XT2
VSSBU
VDDBU
P90/A0
P91/A1
P92/A2/INTP5
P93/A3/INTP6
P94/A4/TO2
P95/A5/TO3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75 PDH4/A20
74 PDH3/A19
73 PDH2/A18
72 PDH1/A17
71 PDH0/A16
70 PDL15/AD15
69 PDL14/AD14
68 PDL13/AD13
67 PDL12/AD12
66 PDL11/AD11
65 PDL10/AD10
64 EVDD
63 EVSS
62 IC/FLMD0Notes 2, 3
61 PDL9/AD9
60 PDL8/AD8
59 PDL7/AD7
58 PDL6/AD6
57 PDL5/AD5/FLMD1Note 2
56 PDL4/AD4
55 PDL3/AD3
54 PDL2/AD2
53 PDL1/AD1
52 PDL0/AD0
51 PCT7
Notes 1. SCL and SDA are valid only for the µPD703201Y and 70F3201Y.
2. FLMD0 and FLMD1 are valid only for the µPD70F3201 and 70F3201Y.
3. IC:
Connect directly to VSS (µPD703201, 703201Y).
FLMD0: Connect to VSS in normal mode (µPD70F3201, 70F3201Y).
Preliminary Product Information U15436EJ1V0PM
3


3Pages


UPD70F3201 電子部品, 半導体
µPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
PIN IDENTIFICATION
A0 to A23:
AD0 to AD15:
ADTRG:
ANI0 to ANI15:
ANO0, ANO1:
ASTB:
AVDD:
AVREF0, AVREF1:
AVSS:
CLKOUT:
CS0 to CS3:
EVDD:
EVSS:
FLMD0, FLMD1:
HLDAK:
HLDRQ:
IC:
INTP0 to INTP6:
INTP00, INTP01,:
INTP10, INTP11
NMI:
P00 to P05:
P20 to P22:
P30 to P32:
P40 to P46:
P70 to P715:
P80, P81:
P90 to P915:
Address bus
Address/data bus
AD trigger input
Analog input
Analog output
Address strobe
Analog VDD
Analog reference voltage
Analog VSS
Clock output
Chip select
Power supply for port
Ground for port
Flash programming mode
Hold acknowledge
Hold request
Internally connected
Interrupt request from peripherals
Interrupt request to timer
Non-maskable interrupt request
Port 0
Port 2
Port 3
Port 4
Port 7
Port 8
Port 9
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PCD1 to PCD3:
PCM0 to PCM5:
PCS0 to PCS7:
PCT0 to PCT7:
PDH0 to PDH7:
PDL0 to PDL15:
RD:
RESET:
RXD0, RXD1:
SCK0 to SCK4:
SCL:
SDA:
SI0 to SI4:
SO0 to SO4:
TCLR0, TCLR1:
TI0 to TI5:
TO0 to TO5:
TXD0, TXD1:
VDD:
VDDBU:
VSS:
VSSBU:
WAIT:
WR0:
WR1:
X1, X2:
XT1, XT2:
Port CD
Port CM
Port CS
Port CT
Port DH
Port DL
Read
Reset
Receive data
Serial clock
Serial clock
Serial data
Serial input
Serial output
Timer clear input
Timer input
Timer output
Transmit data
Power supply
Power supply for backup
Ground
Ground for backup
Wait
Write strobe low level data
Write strobe high level data
Crystal for main clock
Crystal for subclock
6 Preliminary Product Information U15436EJ1V0PM

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD70F3201

(UPD70F3201 / UPD70F3204) 32-Bit Single-Chip Microcontrollers

NEC Electronics
NEC Electronics
UPD70F3201

32-BIT SINGLE-CHIP MICROCONTROLLERS

NEC
NEC
UPD70F3201

32-BIT SINGLE-CHIP MICROCONTROLLERS

NEC
NEC
UPD70F3201Y

32-BIT SINGLE-CHIP MICROCONTROLLERS

NEC
NEC


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