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ISL6742 の電気的特性と機能

ISL6742のメーカーはIntersil Corporationです、この部品の機能は「Advanced Double-Ended PWM Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6742
部品説明 Advanced Double-Ended PWM Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6742 Datasheet, ISL6742 PDF,ピン配置, 機能
®
Data Sheet
July 25, 2005
ISL6742
www.DataSheet4U.com
FN9183.1
Advanced Double-Ended PWM Controller
The ISL6742 is a high-performance double-ended PWM
controller with advanced synchronous rectifier control and
current limit features. It is suitable for both current- and
voltage-mode control methods.
The ISL6742 includes complemented PWM outputs for
synchronous rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the main outputs using an external control voltage.
Its advanced current sensing circuitry employs sample and
hold methods to provide a precise average current signal.
Suitable for average current limiting, a technique which
virtually eliminates the current tail-out common to peak
current limiting methods, it is also applicable to current
sharing circuits and average current mode control.
This advanced BiCMOS design features an adjustable
oscillator frequency up to 2MHz, internal over-temperature
protection, precision deadtime control, and short
propagation delays. Additionally, Multi-Pulse Suppression
ensures alternating output pulses at low duty cycles where
pulse skipping may occur.
Ordering Information
TEMP. RANGE
PKG. DWG.
PART NUMBER
(°C)
PACKAGE
#
ISL6742AAZA
(See Note)
-40 to 105
16 Ld QSOP M16.15A
(Pb-free)
Add -T suffix to part number for tape and reel packaging
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL6742 (QSOP)
TOP VIEW
VREF 1
VERR 2
RTD 3
CT 4
FB 5
RAMP 6
CS 7
IOUT 8
16 SS
15 VADJ
14 VDD
13 OUTA
12 OUTB
11 OUTAN
10 OUTBN
9 GND
Features
• Synchronous Rectifier Control Outputs with Adjustable
Delay/Advance
• Adjustable Average Current Signal
• 3% Tolerance Cycle-by-Cycle Peak Current Limit
• Fast Current Sense to Output Delay
• Adjustable Oscillator Frequency Up to 2MHz
• Adjustable Deadtime Control
• Voltage- or Current-Mode Operation
• Separate RAMP and CS Inputs for Voltage Feed Forward
or Current-Mode Applications
• Tight Tolerance Error Amplifier Reference Over Line,
Load, and Temperature
• 175µA Start-up Current
• Supply UVLO
• Adjustable Soft-Start
• 70ns Leading Edge Blanking
• Multi-Pulse Suppression
• Internal Over Temperature Protection
• Pb-free and ELV, WEEE, RoHS Compliant
Applications
• Half-Bridge, Full-Bridge, Interleaved Forward, and Push-
Pull Converters
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6742 pdf, ピン配列
Typical Application - Telecom Primary Side Control Half-Bridge Converter with Synchronous Rectification
VIN+
C1
36-75V
VIN-
C2
CR3
C3
Q1
R1 Q2
C7
C4
C5
U1
HIP2100
VDD LO
HB VSS
HO LI
HS HI
R3
R2
Q7 C8
C15
R13
T2
C14
T1
R17
C17
R9
CR1
CR2
R8
R7
Q3 Q5
Q4 Q6
C13
R5
R6
U2
ISL6742
1 VREF
SS 16
2 VERR
VADJ 15
3 RTD
VDD 14
4 CT
OUTA 13
5 FB
OUTB 12
6 RAMP
OUTAN 11
7 CS
OUTBN 10
8 IOUT
GND 9
R11
VR1
C6
R4 C9
R10
C10
C11
R12
C16
R16
EL7212
U6
R15
CR4
R14
C12
L1 +VOUT
+
C22
C23
RTN
R25
T3
C18
EL7212
U5
C24
R19
R18
+VOUT
R23
R20
C20
R22
C19
U3
VR2
R21
C21
U4
TL431
R24


3Pages


ISL6742 電子部品, 半導体
ISL6742
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. Refer to Block Diagrawmwawn.dDTaytapiSchael Aept4pUlic.caotiomn
schematic. 9V < VDD < 20V, RTD = 10.0k, CT = 470pF, TA = -40°C to 105°C (Note 3), Typical values are at
TA = 25°C (Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RAMP
RAMP Sink Current Device Impedance
RAMP to PWM Comparator Offset
Bias Current
Clamp Voltage
VRAMP = 1.1V
TA = 25°C
VRAMP = 0.3V
(Note 4)
- - 20
65 80 95 mV
-5.0 - -2.0 µA
6.5 - 8.0 V
SOFT-START
Charging Current
SS = 3V
-60 -70 -80 µA
SS Clamp Voltage
4.410
4.500
4.590
V
SS Discharge Current
SS = 2V
10 -
- mA
Reset Threshold Voltage
ERROR AMPLIFIER
TA = 25°C
0.23 0.27 0.33
V
Input Common Mode (CM) Range
(Note 4)
0 - VREF V
GBWP
(Note 4)
5 - - MHz
VERR VOL
VERR VOH
VERR Pull-Up Current Source
ILOAD = 2mA
ILOAD = 0mA
VERR = 2.50V
- - 0.4 V
4.20 - - V
0.8 1.0 1.3 mA
EA Reference
EA Reference + EA Input Offset Voltage
TA = 25°C
0.594
0.590
0.600
0.600
0.606
0.612
V
V
PULSE WIDTH MODULATOR
Minimum Duty Cycle
VERR < 0.6V
- - 0%
Maximum Duty Cycle (per half-cycle)
VERR = 4.20V, VRAMP = 0V,
VCS = 0V (Note 5)
RTD = 2.00k, CT = 220pF
- 94 - %
- 97 - %
RTD = 2.00k, CT = 470pF
- 99 - %
Zero Duty Cycle VERR Voltage
0.85 - 1.20 V
VERR to PWM Comparator Input Offset
VERR to PWM Comparator Input Gain
TA = 25°C
0.7
0.31
0.8
0.33
0.9
0.35
V
V/V
Common Mode (CM) Input Range
(Note 4)
0 - 4.45 V
OSCILLATOR
Frequency Accuracy, Overall
(Note 4)
165 183 201 kHz
-10 - +10 %
Frequency Variation with VDD
Temperature Stability
TA = 25°C, (F20V- - F10V)/F10V
VDD = 10V, |F-40°C - F0°C|/F0°C
(Note 4)
-
0.3 1.7
%
- 4.5 -
%
|F0°C - F105°C|/F25°C
(Note 4)
- 1.5 -
%
Charge Current
Discharge Current Gain
TA = 25°C, VCS = 1.8V
-193
19
-200
21
-207
23
µA
µA/µA
CT Valley Voltage
Static Threshold
0.75 0.80 0.88
V
CT Peak Voltage
Static Threshold
2.75 2.80 2.88
V
6 FN9183.1
July 25, 2005

6 Page



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共有リンク

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