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UPD703213 の電気的特性と機能

UPD703213のメーカーはNECです、この部品の機能は「32-Bit Single-Chip Microcontrollers」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD703213
部品説明 32-Bit Single-Chip Microcontrollers
メーカ NEC
ロゴ NEC ロゴ 




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UPD703213 Datasheet, UPD703213 PDF,ピン配置, 機能
User’s Manual
www.DataSheet4U.com
V850ES/KF1TM, V850ES/KG1TM, V850ES/KJ1TM
32-Bit Single-Chip Microcontrollers
Hardware
V850ES/KF1:
µPD703208
µPD703208(A)
µPD703208Y
µPD703208Y(A)
µPD703209
µPD703209(A)
µPD703209Y
µPD703209Y(A)
µPD703210
µPD703210(A)
µPD703210Y
µPD703210Y(A)
µPD70F3210
µPD70F3210(A)
µPD70F3210Y
µPD70F3210Y(A)
V850ES/KG1:
µPD703212
µPD703212(A)
µPD703212Y
µPD703212Y(A)
µPD703213
µPD703213(A)
µPD703213Y
µPD703213Y(A)
µPD703214
µPD703214(A)
µPD703214Y
µPD703214Y(A)
µPD70F3214
µPD70F3214(A)
µPD70F3214Y
µPD70F3214Y(A)
Document No. U15862EJ3V0UD00 (3rd edition)
Date Published January 2003 N CP(K)
Printed in Japan
2002
V850ES/KJ1:
µPD703216
µPD703216(A)
µPD703216Y
µPD703216Y(A)
µPD703217
µPD703217(A)
µPD703217Y
µPD703217Y(A)
µPD70F3217
µPD70F3217(A)
µPD70F3217Y
µPD70F3217Y(A)

1 Page





UPD703213 pdf, ピン配列
NOTES FOR CMOS DEVICES
www.DataSheet4U.com
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
V850 Series, V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are trademarks of NEC Electronics
Corporation.
User’s Manual U15862EJ3V0UD
3


3Pages


UPD703213 電子部品, 半導体
Major Revisions in This Edition (1/2)
www.DataSheet4U.com
Pages
Description
Throughout Addition of the following special quality grade products.
µPD703208(A), 703208Y(A), 703209(A), 703209Y(A), 703210(A), 703210Y(A), 703212(A), 703212Y(A),
703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A),
70F3210Y(A), 70F3214(A), 70F3214Y(A), 70F3217(A), 70F3217Y(A)
p. 33
Addition of Caution in 1.2.4 Pin configuration (top view) (V850ES/KF1)
p. 41
Addition of Caution in 1.3.4 Pin configuration (top view) (V850ES/KG1)
p. 49
Addition of Caution in 1.4.4 Pin configuration (top view) (V850ES/KJ1)
p. 55
Addition of description in CHAPTER 2 PIN FUNCTIONS and addition of Table 2-1 Pin I/O Buffer Power
Supplies
pp.93, 95 Modification of description on recommended connection of P70 to P77, P78 to P715, IC, VPP, and XT1 in 2.4 Pin
I/O Circuits and Recommended Connection of Unused Pins
p. 134
Modification of description in 3.4.8 (2) Access to special on-chip peripheral I/O registers
p. 285
Modification of description in 5.11 Bus Timing
p. 291
Addition of 5.12 Cautions
p. 292
Addition of description on the main clock oscillator in 6.1 Overview
p. 293
Addition of description in 6.2 (1) Main clock oscillator
p. 296
Addition of Caution 3 in 6.3 (1) Processor clock control register (PCC)
p. 302
Addition of description in CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05
p. 306
Modification of description of Caution 4 in 7.2 (2) 16-bit timer capture/compare register 0n0 (CR0n0)
p. 307
Modification of description of Caution 4 in 7.2 (3) 16-bit timer capture/compare register 0n1 (CR0n1)
p. 311
Modification of description of Caution 1 in 7.3 (3) 16-bit timer output control register 0n (TOC0n)
p. 319
Addition of setting procedures and modification of description in 7.4.1 Operation as interval timer (16 bits)
p. 322
Addition of setting procedures in 7.4.2 PPG output operation
p. 324
Addition of Figure 7-6 Configuration of PPG Output
p. 325
Addition of Figure 7-7 PPG Output Operation Timing
p. 326
Addition of setting procedures in 7.4.3 Pulse width measurement
p. 334
Addition of setting procedures and addition of Caution 2 in 7.4.4 Operation as external event counter (16-bit
timer/event counters 00, 01, 04 and 05 only)
p. 337
Addition of setting procedures and addition of Caution in 7.4.5 Square-wave output operation (16-bit
timer/event counters 04 and 05 only)
p. 340
Addition of setting procedures in 7.4.6 One-shot pulse output operation
p. 340
Addition of Caution 2 in 7.4.6 (1) One-shot pulse output with software trigger
p. 342
Addition of Caution 2 in 7.4.6 (2) One-shot pulse output with external trigger
p. 349
Addition of Caution in 7.4.7 (10) (b) When setting CR0n0, CR0n1 to compare mode
p. 350
Addition of description in CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
p. 369
Addition of description in CHAPTER 9 8-BIT TIMERS H0 AND H1
p. 373
Addition of Caution 3 in 9.3 (1) (a) 8-bit timer H mode register 0 (TMHMD0)
p. 374
Addition of Caution 3 in 9.3 (1) (b) 8-bit timer H mode register 1 (TMHMD1)
p. 386
Addition of Caution 2 in Figure 9-7 Transfer Timing
p. 388
Addition of Caution 4 in 9.4.3 (4) Timing chart
p. 427
Addition of 13.4 Relationship Between Analog Input Voltage and A/D Conversion Result
6 Users Manual U15862EJ3V0UD

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD703210

32-Bit Single-Chip Microcontrollers

NEC
NEC
UPD703210A

32-Bit Single-Chip Microcontrollers

NEC
NEC
UPD703210Y

32-Bit Single-Chip Microcontrollers

NEC
NEC
UPD703210YA

32-Bit Single-Chip Microcontrollers

NEC
NEC


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