IDT5T9306 データシート ( 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER II )

部品番号

IDT5T9306

部品説明

2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER II

メーカ

Integrated Device Technology

ロゴ

このページの下部にプレビューとIDT5T9306ダウンロード（pdfファイル）リンクがあります。

Total 13 pages

No Preview Available !

IDT5T9306 Datasheet, IDT5T9306 PDF,ピン配置, 機能

2.5V LVDS 1:6 CLOCK BUFFER

TERABUFFER™ II

www.DataSheet4U.com

IDT5T9306

FEATURES:

• Guaranteed Low Skew < 25ps (max)

• Very low duty cycle distortion < 125ps (max)

• High speed propagation delay < 1.75ns (max)

• Additive phase jitter, RMS 0.159ps (typical) @ 125MHz

• Up to 1GHz operation

• Selectable inputs

• Hot insertable and over-voltage tolerant inputs

• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),

CML, or LVDS input interface

• Selectable differential inputs to six LVDS outputs

• Power-down mode

• 2.5V VDD

• Available in VFQFPN package

DESCRIPTION:

TheIDT5T93062.5Vdifferential clockbufferisauser-selectabledifferential

inputtosixLVDSoutputs. ThefanoutfromadifferentialinputtosixLVDSoutputs

reduces loading on the preceding driver and provides an efficient clock

distributionnetwork. TheIDT5T9306canactasatranslatorfromadifferential

HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to

LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to

translate to LVDS outputs. The redundant input capability allows for an

asynchronous change-over from a primary clock source to a secondary clock

source. Selectable reference inputs are controlled by SEL.

The IDT5T9306 outputs can be asynchronously enabled/disabled. When

disabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiplepower

and grounds reduce noise.

APPLICATIONS:

• Clock distribution

FUNCTIONAL BLOCK DIAGRAM

A1 1

SEL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

IDT™ / ICS™ LVDS CLOCK BUFFER TERABUFFER™ II

IDT5T9306 REV. A OCTOBER 23, 2007

1 Page

IDT5T9306

2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Description

Max

VDD Power Supply Voltage

–0.5 to +3.6

VI Input Voltage

–0.5 to +3.6

VO Output Voltage(2)

–0.5 to VDD +0.5

TSTG Storage Temperature

–65 to +150

TJ Junction Temperature

150

Unit

°C

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Not to exceed 3.6V.

www.DataSheet4U.com

CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)

Symbol

Parameter

CIN Input Capacitance

Min Typ. Max. Unit

— — 3 pF

NOTE:

1. This parameter is measured at characterization but not tested

RECOMMENDED OPERATING RANGE

Symbol

VDD

Description

Ambient Operating Temperature

Internal Power Supply Voltage

Min. Typ. Max.

–40 +25 +85

2.3 2.5 2.7

Unit

°C

PIN DESCRIPTION

Symbol I/O

Type Description

A[1:2] I Adjustable(1,4) Clock input. A[1:2] is the "true" side of the differential clock input.

A[1:2] I Adjustable(1,4) Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the

desired toggle voltage for A[1:2]:

3.3V LVTTL VREF = 1650mV

2.5V LVTTL VREF = 1250mV

G I LVTTL Gate control for differential outputs Q1 and Q1 through Q6 and Q6. When Gis LOW, the differential outputs are active. When Gis

HIGH, the differential outputs are asynchronously driven to the level designated by GL(2).

GL I

LVTTL

Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"

outputs disable LOW and "complementary" outputs disable HIGH.

Qn O

LVDS Clockoutputs

Qn O

LVDS Complementaryclockoutputs

SEL I

PD I

VDD

LVTTL

PWR

Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1.

Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both

"true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)

Power supply for the device core and inputs

GND PWR Power supply return for all power

N C No connect; recommended to connect to GND

NOTES:

1. Inputs are capable of translating the following interface standards:

Single-ended 3.3V and 2.5V LVTTL levels

Differential HSTL and eHSTL levels

Differential LVEPECL (2.5V) and LVPECL (3.3V) levels

Differential LVDS levels

Differential CML levels

2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt

pulses or be able to tolerate them in down stream circuitry.

3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-

up after asserting PD.

4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.

IDT™ / ICS™ LVDS CLOCK BUFFER TERABUFFER™ II

IDT5T9306 REV. A OCTOBER 23, 2007

3Pages

IDT5T9306

2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II

www.DataSheet4U.com

DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS

Symbol

Parameter

Value

Units

VDIF Input Signal Swing(1)

400 mV

VX Differential Input Signal Crossing Point(2)

1.2 V

DH Duty Cycle

50 %

VTHI InputTimingMeasurementReferenceLevel(3)

Crossing Point

tR, tF Input Signal Edge Rate(4)

2 V/ns

NOTES:

1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)

specification under actual use conditions.

2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under

actual use conditions.

3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.

4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.

AC DIFFERENTIAL INPUT SPECIFICATIONS(1)

Symbol

Parameter

Min. Typ.

Max

Unit

VDIF AC Differential Voltage(2)

0.1 — 3.6

VIX DifferentialInputCrosspointVoltage

0.05 —

VDD

VCM Common Mode Input Voltage Range(3)

0.05 —

VDD

VIN InputVoltage

- 0.3 +3.6 V

NOTES:

1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been met or exceeded.

2. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage

must be achieved to guarantee switching to a new state.

3. VCM specifies the maximum allowable range of (VTR + VCP) /2.

POWER SUPPLY CHARACTERISTICS FOR LVDS OUTPUTS(1)

Symbol

IDDQ

Parameter

Quiescent VDD Power Supply Current

ITOT Total Power VDD Supply Current

IPD Total Power Down Supply Current

Test Conditions

VDD = Max., All Input Clocks = LOW(2)

Outputs enabled

VDD = 2.7V., FREFERENCE CLOCK = 1GHz

PD = LOW

Typ.

—

NOTES:

1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.

2. The true input is held LOW and the complementary input is held HIGH.

Max

240

250

Unit

IDT™ / ICS™ LVDS CLOCK BUFFER TERABUFFER™ II

IDT5T9306 REV. A OCTOBER 23, 2007

6 Page

ページ

合計 : 13 ページ

PDF
ダウンロード

[ IDT5T9306 datasheet.PDF ]

IDT5T9306 の電気的特性と機能

製品の詳細 ( Datasheet PDF )

部品紹介

共有リンク

おすすめデータシート