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PDF ISL62872 Data sheet ( Hoja de datos )
| Número de pieza | ISL62872 | |
| Descripción | PWM DC/DC Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL62871, ISL62872
August 14, 2008
www.DataSheet4U.com
FN6707.0
PWM DC/DC Controller With VID Inputs
For Portable GPU Core-Voltage Regulator
The ISL62871 and ISL62872 IC’s are Single-Phase
Synchronous-Buck PWM voltage regulators featuring
Intersil’s Robust Ripple Regulator (R3) Technology™. The
wide 3.3V to 25V input voltage range is ideal for systems
that run on battery or AC-adapter power sources. The
ISL62871 and ISL62872 are low-cost solutions for
applications requiring dynamically selected slew-rate
controlled output voltages. The soft-start and dynamic
setpoint slew-rates are capacitor programmed. Voltage
identification logic-inputs select two (ISL62871) or four
(ISL62872) resistor-programmed setpoint reference voltages
that directly set the output voltage of the converter between
0.5V to 1.5V, and up to 3.3V using a feedback voltage
divider. Optionally, an external reference such as the DAC
output from a microcontroller, can be used by either IC to
program the setpoint reference voltage, and still maintain the
controlled slew-rate features. Robust integrated MOSFET
drivers and Schottky bootstrap diode reduce the
implementation area and lower component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The PWM
frequency is 300kHz during static operation, becoming
variable during changes in load, setpoint voltage, and input
voltage when changing between battery and AC-adapter
power. The modulators ability to change the PWM switching
frequency during these events in conjunction with external
loop compensation produces superior transient response.
For maximum efficiency, the converter automatically enters
diode-emulation mode (DEM) during light-load conditions
such as system standby.
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Output Load up to 30A
• Extremely Flexible Output Voltage Programmability
- 2-Bit VID (ISL62872) Selects Four Independent
Setpoint Voltages
- 1-Bit VID (ISL62871) Selects Two Independent Setpoint
Voltages
- Simple Resistor Programming of Setpoint Voltages
- Accepts External Setpoint Reference Such as DAC
• ±0.75% System Accuracy: -10°C to +100°C
• One Capacitor Programs Soft-start and Setpoint Slew-rate
• Fixed 300kHz PWM Frequency in Continuous Conduction
• External Compensation Affords Optimum Control Loop
Tuning
• Automatic Diode Emulation Mode for Highest Efficiency
• Integrated High-current MOSFET Drivers and Schottky
Boot-Strap Diode for Optimal Efficiency
• Choice of Overcurrent Detection Schemes
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Power-Good Monitor for Soft-Start and Fault Detection
• Fault Protection
- Undervoltage
- Overvoltage
- Overcurrent (DCR-Sense or Resistive-Sense
Capability)
- Over-Temperature Protection
- Fault Identification by PGOOD Pull-Down Resistance
• Pb-Free (RoHS compliant)
Applications
• Mobile PC Graphical Processing Unit VCC rail
• Mobile PC I/O Controller Hub (ICH) VCC rail
• Mobile PC Memory Controller Hub (GMCH) VCC rail
• Built-in voltage margin for system-level test
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL62871, ISL62872
Application Schematics (Continued)
www.DataSheet4U.com
+5V
GPIO
RVCC
CPVCC
CVCC
GND
EN
VID0
SREF
1
2
3
4
BOOT
12
UGATE
11
PHASE
10
OCSET
9
CBOOT
QHS
QLS
VIN
3.3V TO 25V
CINC
CINB
LO
COCSET
VOUT
0.5V TO 3.3V
COC
COB
RSET1
VCC
RCOMP
CCOMP
RO
RFB
GPIO
FIGURE 4. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
+5V
GPIO
RVCC
CPVCC
CVCC
GND
EN
VID0
SREF
1
2
3
4
BOOT
12
UGATE
11
PHASE
10
OCSET
9
CBOOT
QHS
LO
QLS
VIN
3.3V TO 25V
CINC
CINB
RSNS
COCSET
VOUT
0.5V TO 3.3V
COC
COB
RSET1
VCC
RCOMP
CCOMP
RO
RFB
GPIO
FIGURE 5. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
5 FN6707.0
August 14, 2008
5 Page 
ISL62871, ISL62872
VSET(x) where (x) is the first, second, third, or fourth setpoint
reference voltage where:
- VSET1 < VSET2 < VSET3 < VSET4
- VOUT1 < VOUT2 < VOUT3 < VOUT4
The VSET1 setpoint is fixed at 500mV because it
corresponds to the closure of internal switch SW0 that
configures the VSET amplifier as a unity-gain voltage
follower for the 500mV voltage reference VREF.
A feedback voltage-divider network may be required to
achieve the desired reference voltages. Using the feedback
voltage-divider allows the maximum output voltage of the
converter to be higher than the 1.5V maximum setpoint
reference voltage that can be programmed on the SREF pin.
Likewise, the feedback voltage-divider allows the minimum
output voltage of the converter to be higher than the fixed
500mV setpoint reference voltage of VSET1. Scale the
voltage-divider network such that the voltage VFB equals the
voltage VSREF when the converter output voltage is at the
desired level. The voltage-divider relation is given in
Equation 1:
VFB
=
VO
U
T
⋅
----------R----O-----F---S-----------
RFB + ROFS
(EQ. 1)
Where:
- VFB = VSREF
- RFB is the loop-compensation feedback resistor that
connects from the FB pin to the converter output
- ROFS is the voltage-scaling programming resistor that
connects from the FB pin to the GND pin
The attenuation of the feedback voltage divider is written as:
K
=
V-----S----R----E----F---(---l-i--m----)
VOUT(lim)
=
----------R----O-----F---S-----------
RFB + ROFS
(EQ. 2)
Where:
- K is the attenuation factor
- VSREF(lim) is the VSREF voltage setpoint of either
500mV or 1.50V
- VOUT(lim) is the output voltage of the converter when
VSREF = VSREF(lim)
Since the voltage-divider network is in the feedback path, all
output voltage setpoints will be attenuated by K, so it follows
that all of the setpoint reference voltages will be attenuated
by K. It will be necessary then to include the attenuation
factor K in all the calculations for selecting the RSET
programming resistors.
The value of offset resistor ROFS can be calculated only
after the value of loop-compensation resistor RFB has been
determined. The Calculation of ROFS is written as
Equation 3:
ROFS
=
---V-----S----E----T---(--x---)----⋅---R----F----B-----
VOUT – VSET(x)
(EQ. 3)
The setpoint reference voltages arewpwrwog.DraamtamSheedewt4itUh.com
resistors that use the naming convention RSET(x) where (x)
is the first, second, third, or fourth programming resistor
connected in series starting at the SREF pin and ending at
the GND pin. When one of the internal switches closes, it
connects the inverting input of the VSET amplifier to a
specific node among the string of RSET programming
resistors. All the resistors between that node and the SREF
pin serve as the feedback impedance RF of the VSET
amplifier. Likewise, all the resistors between that node and
the GND pin serve as the input impedance RIN of the VSET
amplifier. Equation 4 gives the general form of the gain
equation for the VSET amplifier:
VSET(X )
=
VREF
⋅
⎛
⎜1
⎝
+
R--R---I-F-N--⎠⎟⎞
(EQ. 4)
Where:
- VREF is the 500mV internal reference of the IC
- VSET(x) is the resulting setpoint reference voltage that
appears at the SREF pin
Calculating Setpoint Voltage Programming
Resistor Values for ISL62872
TABLE 1. ISL62872 VID TRUTH TABLE
VID STATE
RESULT
VID1
VID0
CLOSE
VSREF
VOUT
1
1
SW0
VSET1
VOUT1
1
0
SW1
VSET2
VOUT2
0
1
SW2
VSET3
VOUT3
0
0
SW3
VSET4
VOUT4
First, determine the attenuation factor K. Next, assign an
initial value to RSET4 of approximately 100kΩ then calculate
RSET1, RSET2, and RSET3 using Equations 5, 6, and 7
respectively. The equation for the value of RSET1 is written
as Equation 5:
RSET1 = -R----S----E----T----4----⋅---K----V-V----SR----E-E--T--F--4--⋅--⋅-K--(---VK----SV----E-S---T-E--2-T----2----–-----V----R----E----F----)
(EQ. 5)
The equation for the value of RSET2 is written as Equation 6:
RSET2 = -R----S----E----T----4----⋅---K----V-K----S-V---E-S--T--E--4--T--⋅-2--(---⋅K---K-V---V--S--S--E--E-T---T-3---3-–-----K----V-----S----E---T----2----)
(EQ. 6)
The equation for the value of RSET3 is written as Equation 7:
RSET3
=
R-----S----E----T----4----⋅---(--K-----V----S----E----T----4----–----K-----V----S----E----T----3---)
KVSET3
(EQ. 7)
The sum of all the programming resistors should be
approximately 300kΩ as shown in Equation 8 otherwise
adjust the value of RSET4 and repeat the calculations.
RSET1 + RSET2 + RSET3 + RSET4 ≅ 300kΩ
(EQ. 8)
Equations 9, 10, 11 and 12 give the specific VSET gain
equations for the ISL62872 setpoint reference voltages.
11 FN6707.0
August 14, 2008
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ISL62872.PDF ] | |
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