DataSheet.jp

HYMD512G726A8M-M の電気的特性と機能

HYMD512G726A8M-MのメーカーはHynix Semiconductorです、この部品の機能は「Low Profile Registered DDR SDRAM DIMM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HYMD512G726A8M-M
部品説明 Low Profile Registered DDR SDRAM DIMM
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




このページの下部にプレビューとHYMD512G726A8M-Mダウンロード(pdfファイル)リンクがあります。
Total 16 pages

No Preview Available !

HYMD512G726A8M-M Datasheet, HYMD512G726A8M-M PDF,ピン配置, 機能
12ww8wM.Daxta7Sh2eebt4Uit.csom
Low Profile Registered DDR SDRAM DIMM
HYMD512G726A(L)8M-M/K/H/L
DESCRIPTION
Preliminary
Hynix HYMD512G726A(L)8M-M/K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM
Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix
HYMD512G726A(L)8M-M/K/H/L series consists of eighteen 64Mx8 DDR SDRAM in 400mil TSOP II packages on a
184pin glass-epoxy substrate. Hynix HYMD512G726A(L)8M-M/K/H/L series provide a high performance 8-byte inter-
face in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD512G726A(L)8M-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD512G726A(L)8M-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 1GB (128M x 72) Low Profile Registered DDR DIMM • Fully differential clock operations (CK & /CK) with
based on 64Mx8 DDR SDRAM
125MHz/133MHz
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Error Check Correction (ECC) Capability
• Programmable CAS Latency 2 / 2.5 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Registered inputs with one-clock delay
• tRAS Lock-out function supported
• Phase-lock loop (PLL) clock driver to reduce loading • Internal four bank operations with single pulsed RAS
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• Auto refresh and self refresh supported
• All inputs and outputs are compatible with SSTL_2
interface
• 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD512G726A(L)8M-M
HYMD512G726A(L)8M-K
HYMD512G726A(L)8M-H
HYMD512G726A(L)8M-L
Power Supply
VDD=2.5V
VDDQ=2.5V
Clock Frequency
133MHz (*DDR266 2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
125MHz (*DDR200)
Interface
Form Factor
SSTL_2
184pin Registered DIMM
5.25 x 1.2 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Jan. 2003
1

1 Page





HYMD512G726A8M-M pdf, ピン配列
www.DataSheet4U.com
HYMD512G726A(L)8M-M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
./RCS1
/RCS0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS0
/CS1
BA0-BA1
A0-A12
/RAS
/CAS
CKE0
CKE1
/WE
PCK
/PCK
R
E
G
/CS DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
D9
DQS
/CS DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D10
/CS DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D11
/CS DQS
D3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D12
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D13
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D16
/CS DQS
D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS DQS
D17
/RCS0 -->/CS0 : SDRAMs D0-D8
/RCS1-->/CS1 : SDRAMs D9 - D17
RBA0-RBA1--> : BA0-BA1:SDRAMs D0-D17
RA0 -R A12 -->A0 - A12 : SDRAMs D0 - D17
/RRAS --> /RAS : SDRAMs D0 - D17
/RCAS --> /CAS : SDRAMs D0 - D17
RCKE0 --> CKE : SDRAMs D0 - D8
RCKE1 --> CKE : SDRAMs D9-D17
/RWE --> /WE : SDRAMs D0 - D17
/RESET
CK0, /CK0 --------- PLL*
* Wire per clock loading table/wiring diagrams
Serial PD
SCL
WP A0 A1 A2
SDA
VDDSPD
VDDQ
VDD
VREF
VSS
VDDID
SA0 SA1 SA2
..
==
....
.
=..
.
=
.
SPD
D0 - D17
D0 - D17
D0 - D17
D0 - D17
Strap:see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ/DQS resistors should be 18 Ohms.
4. VDDID strap connections(for memory device VDD, VDDQ);
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD=VDDQ
5. /RS0 and /RS1 alternate btw the back and front sides of the DIMM
6. Address and control resistors should be 22 Ohms
Rev. 0.1/Jan. 2003
3


3Pages


HYMD512G726A8M-M 電子部品, 半導体
CAPACITANCE (TA=25oC, f=100MHz )
www.DataSheet4U.com
HYMD512G726A(L)8M-M/K/H/L
Parameter
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Data Input / Output Capacitance
Data Input / Output Capacitance
Pin
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE0, CKE1
CS0, CS1
CK0, /CK0
DM0 ~ DM8
DQ0 ~ DQ63, DQS0 ~ DQS8
CB0 ~ CB7
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIO1
CIO2
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Output
VTT
RT=50
Zo=50
CL=30pF
VREF
Rev. 0.1/Jan. 2003
6

6 Page



ページ 合計 : 16 ページ
 
PDF
ダウンロード
[ HYMD512G726A8M-M データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
HYMD512G726A8M-H

Low Profile Registered DDR SDRAM DIMM

Hynix Semiconductor
Hynix Semiconductor
HYMD512G726A8M-J

Low Profile Registered DDR SDRAM DIMM

Hynix Semiconductor
Hynix Semiconductor
HYMD512G726A8M-K

Low Profile Registered DDR SDRAM DIMM

Hynix Semiconductor
Hynix Semiconductor
HYMD512G726A8M-M

Low Profile Registered DDR SDRAM DIMM

Hynix Semiconductor
Hynix Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap