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PDF HYMD264G726BM4M-H Data sheet ( Hoja de datos )

Número de pieza HYMD264G726BM4M-H
Descripción Low Profile Registered DDR SDRAM DIMM
Fabricantes Hynix Semiconductor　
Logotipo Hynix Semiconductor Logotipo



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Revision History
Revision No.
0.1
0.2
w6w4wM.Daxta7Sh2eebt4iUt.csom
Low Profile Registered DDR SDRAM DIMM
HYMD264G726B(L)4M-M/K/H/L
History
Defined Target Spec.
Defined Cap. Value
Draft Date
Oct. 2002
Dec. 2003
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/ Dec. 2003
1

1 page




HYMD264G726BM4M-H pdf
ABSOLUTE MAXIMUM RATINGS
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HYMD264G726B(L)4M-M/K/H/L
Parameter
Operating Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
Symbol
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
18
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
Unit
oC
oC
V
V
V
mA
W
oC / Sec
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol Min Typ.
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
VDD
VDDQ
VIH
VIL
VTT
VREF
2.3
2.3
VREF + 0.15
-0.3
VREF - 0.04
0.49*VDDQ
2.5
2.5
-
-
VREF
0.5*VDDQ
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
Max
2.7
2.7
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
Unit
V
V
V
V
V
V
Note
1
2
3
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
0.7
0.5*VDDQ-0.2
VREF - 0.31
VDDQ + 0.6
0.5*VDDQ+0.2
V
V
V
V
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2/ Dec. 2003
5

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HYMD264G726BM4M-H arduino
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HYMD264G726B(L)4M-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
Parameter
Symbol
DDR266(2-2-2)
Min Max
Input Setup Time (fast slew rate) tIS
0.9
-
Input Hold Time (fast slew rate)
tIH
0.9
-
Input Setup Time (slow slew rate) tIS
1.0
-
Input Hold Time (slow slew rate)
tIH
1.0
-
Input Pulse Width
tIPW
2.2
Write DQS High Level Width
tDQSH 0.35
-
Write DQS Low Level Width
tDQSL 0.35
-
Clock to First Rising edge of
DQS-In
tDQSS 0.72 1.28
Data-In Setup Time to DQS-In
(DQ & DM)
tDS 0.5
-
Data-in Hold Time to DQS-In (DQ
& DM)
tDH
0.5
-
DQ & DM Input Pulse Width
tDIPW 1.75
-
Read DQS Preamble Time
tRPRE
0.9
1.1
Read DQS Postamble Time
tRPST
0.4
0.6
Write DQS Preamble Setup Time tWPRES 0
-
Write DQS Preamble Hold Time tWPREH 0.25
-
Write DQS Postamble Time
tWPST
0.4
0.6
Mode Register Set Delay
tMRD
2
-
Exit Self Refresh to Any Execute
Command
tXSC
200
-
Average Periodic Refresh Interval tREFI - 15.6
DDR266A
Min Max
0.9 -
0.9 -
1.0 -
1.0 -
2.2
0.35 -
0.35 -
0.75 1.25
0.5 -
0.5 -
1.75
0.9
0.4
0
0.25
0.4
2
-
1.1
0.6
-
-
0.6
-
200 -
- 15.6
DDR266B
Min Max
0.9 -
0.9 -
1.0 -
1.0 -
2.2
0.35 -
0.35 -
0.75 1.25
0.5 -
0.5 -
1.75
0.9
0.4
0
0.25
0.4
2
-
1.1
0.6
-
-
0.6
-
200 -
- 15.6
DDR200
Unit Note
Min Max
1.1 - ns 2,3,5,6
1.1 - ns 2,3,5,6
1.1 - ns 2,4,5,6
1.1 - ns 2,4,5,6
2.5 ns 6
0.35 - CK
0.35 - CK
0.75 1.25 CK
0.6
-
ns
6,7,
11~13
0.6
-
ns
6,7,
11~13
2 - ns
0.9 1.1 CK
0.4 0.6 CK
0 - CK
0.25 - CK
0.4 0.6 CK
2 - CK
200 - CK 8
- 15.6 us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps ps
0.5 0 0
0.4 +50 0
0.3
+100
0
Rev. 0.2/ Dec. 2003
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