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CY14B101Q2 の電気的特性と機能

CY14B101Q2のメーカーはCypress Semiconductorです、この部品の機能は「1 Mbit (128K x 8) Serial SPI nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14B101Q2
部品説明 1 Mbit (128K x 8) Serial SPI nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14B101Q2 Datasheet, CY14B101Q2 PDF,ピン配置, 機能
CY14B101Q1
CY14B101Q2
www.DataSheet4U.com
CY14B101Q3
1 Mbit (128K x 8) Serial SPI nvSRAM
Features
1 Mbit Nonvolatile SRAM
Internally organized as 128K x 8
STORE to QuantumTrap Nonvolatile Elements initiated au-
tomatically on Power Down (AutoStore) or by user using HSB
Pin (Hardware Store) or SPI instruction (Software Store)
RECALL to SRAM initiated on Power Up (Power Up Recall)
or by SPI Instruction (Software RECALL)
Automatic STORE on Power Down with a small Capacitor
High Reliability
Infinite Read, Write, and RECALL Cycles
1 Million STORE cycles to QuantumTrap
Data Retention: 20 Years
High Speed Serial Peripheral Interface (SPI)
40 MHz Clock Rate
Supports SPI Modes 0 (0,0) and 3 (1,1)
Write Protection
Hardware Protection using Write Protect (WP) Pin
Software Protection using Write Disable Instruction
Software Block Protection for 1/4,1/2, or entire Array
Low Power Consumption
Single 3V +20%, –10% Operation
Average VCC current of 10 mA at 40 MHz Operation
Industry Standard Configurations
Industrial Temperature
CY14B101Q1 has identical pin configuration to industry stan-
dard 8-pin NV Memory
8-pin DFN and 16-pin SOIC Packages
RoHS Compliant
Logic Block Diagram
Functional Overview
The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nonvolatile static RAM with a nonvolatile
element in each memory cell. The memory is organized as 128K
words of 8 bits each. The embedded nonvolatile elements incor-
porate the QuantumTrap technology, creating the world’s most
reliable nonvolatile memory. The SRAM provides infinite read
and write cycles, while the QuantumTrap cell provides highly
reliable nonvolatile storage of data. Data transfers from SRAM to
the nonvolatile elements (STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
Both STORE and RECALL operations can also be triggered by
the user.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B101Q1
No
Yes
CY14B101Q2
Yes
Yes
CY14B101Q3
Yes
Yes
No No Yes
VCC
VCAP
CS
WP
SCK
HOLD
SI
Instruction decode
Write protect
Control logic
Quantum Trap
128K X 8
SRAM ARRAY
128K X 8
STORE
RECALL
Instruction
register
Address
Decoder
A0-A16
D0-D7
Data I/O register
Power Control
STORE/RECALL
Control
HSB
SO
Status register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-50091 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 04, 2010

1 Page





CY14B101Q2 pdf, ピン配列
CY14B101Q1
CY14B101Q2
wwCw.YDa1ta4ShBee1t40U1.cQom3
Pinouts
Figure 1. Pin Diagram - 8-Pin DFN[1, 3, 2]
CS
SO
WP
GND
1 CY14B101Q1
2
Top View
3
not to scale
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
VCAP
GND
1 CY14B101Q2
2
Top View
3
not to scale
4
8
7
6
5
VCC
HOLD
SCK
SI
Figure 2. Pin Diagram - 16-Pin SOIC
NC
NC
NC
NC
WP
HOLD
NC
GND
1 16
2 15
3
CY14B101Q3
4
Top View
5 not to scale
14
13
12
6 11
7 10
89
VCC
NC
VCAP
SO
SI
SCK
CS
HSB
Table 1. Pin Definitions
Pin Name
CS
SCK
SI
SO
WP
HOLD
HSB
VCAP
NC
GND
VCC
I/O Type
Input
Input
Input
Output
Input
Input
Input/Output
Power Supply
No Connect
Power Supply
Power Supply
Description
Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
Serial Clock. Runs at speeds up to maximum 40 MHz. All inputs are latched at the rising edge of
this clock. Outputs are driven at the falling edge of the clock.
Serial Input. Pin for input of all SPI instructions and data.
Serial Output. Pin for output of data through SPI.
Write Protect. Implements hardware write protection in SPI.
HOLD Pin. Suspends Serial Operation.
Hardware STORE Busy: A weak internal pull up keeps this pin pulled high. If not used, this pin is
left as No Connect.
Output: Indicates busy status of nvSRAM when LOW.
Input: Hardware STORE implemented by pulling this pin LOW externally.
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to GND.
No Connect: This pin is not connected to the die.
Ground
Power Supply (2.7V to 3.6V)
Notes
1. HSB pin is not available in 8 DFN packages.
2. CY14B101Q1 part does not have VCAP pin and does not support AutoStore.
3. CY14B101Q2 part does not have WP pin
Document #: 001-50091 Rev. *D
Page 3 of 24


3Pages


CY14B101Q2 電子部品, 半導体
CY14B101Q1
CY14B101Q2
wwCw.YDa1ta4ShBee1t40U1.cQom3
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power down.
AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if the user
needs this setting to survive power cycle, a STORE operation
must be performed following Autostore Disable or Enable
operation.
Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from
the factory. In CY14B101Q1, VCAP pin is not present and
AutoStore option is not available. The Autostore Enable and
Disable instructions to CY14B101Q1 are ignored.
Note If AutoStore is disabled and VCAP is not required, leave it
open. VCAP pin must never be connected to GND. Power Up
Recall operation cannot be disabled in any case.
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO) and Serial Clock (SCK) pins.
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides serial
access to nvSRAM through SPI interface. The SPI bus on this
device can run at speeds up to 40 MHz
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using a chip select
pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into nvSRAM on rising edge
of SCK starting from the first rising edge after CS goes active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI Master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and master
may select any of the slave devices using the Chip Select pin.
All the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW. The master
also generates the Serial Clock (SCK) and all the data trans-
mission on SI and SO lines are synchronized with this clock.
SPI Slave
SPI slave device is activated by the master through the Chip
Select line. A slave device gets the Serial Clock (SCK) as an
input from the SPI master and all the communication is synchro-
nized with this clock. SPI slave never initiates a communication
on the SPI bus and acts on the instruction from the master.
CY14B101Q1/CY14B101Q2/CY14B101Q3 operates as a SPI
slave and may share the SPI bus with other SPI slave devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high impedance state.
Note A new instruction must begin with the falling edge of Chip
Select (CS). Therefore, only one opcode can be issued for each
active Chip Select cycle.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the communi-
cation is synchronized with this clock after CS goes LOW.
CY14B101Q1/CY14B101Q2/CY14B101Q3 enables SPI modes
0 and 3 for data communication. In both these modes, the inputs
are latched by the slave device on the rising edge of SCK and
outputs are issued on the falling edge. Therefore, the first rising
edge of SCK signifies the arrival of first bit (MSB) of SPI
instruction on the SI pin. Further, all data inputs and outputs are
synchronized with SCK.
Data Transmission - SI and SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as MOSI (Master Out
Slave In) and SO is referred to as MISO (Master In Slave Out).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 1 Mbit serial nvSRAM requires a 3-byte address for any read
or write operation. However, since the actual address is only 17
bits, it implies that the first seven bits which are fed in are ignored
by the device. Although these seven bits are ‘don’t care’,
Cypress recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
opcodes for memory accesses. In addition to the memory
accesses, it provides additional opcodes for the nvSRAM
specific functions: STORE, RECALL, AutoStore Enable, and
AutoStore Disable. Refer to Table 3 on page 8 for details.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tristated.
Status Register
CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status
register. The bits in the status register are used to configure the
SPI bus. These bits are described in Table 5 on page 9.
Document #: 001-50091 Rev. *D
Page 6 of 24

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共有リンク

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部品番号部品説明メーカ
CY14B101Q1

1 Mbit (128K x 8) Serial SPI nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B101Q2

1 Mbit (128K x 8) Serial SPI nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B101Q3

1 Mbit (128K x 8) Serial SPI nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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