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PDF LC72137M Data sheet ( Hoja de datos )
| Número de pieza | LC72137M | |
| Descripción | PLL Frequency Synthesizer for Electronic Tuning | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : EN5743
CMOS IC
LC72137, 72137M
PLL Frequency Synthesizer
for Electronic Tuning
Overview
The LC72137 and LC72137M are PLL frequency
synthesizers for use in radio/cassette players. They allow
high-performance AM/FM tuners to be implemented
easily.
Features
• High-speed programmable frequency divider
— FMIN: 10 to 160 MHz.....Pulse swallower
(divide-by-two prescaler built in)
— AMIN: 2 to 40 MHz.........Pulse swallower
0.5 to 10 MHz......Direct division
• IF counter
IFIN: 0.4 to 12 MHz................For use as an AM/FM IF
counter
• Reference frequency
— Selectable from one of eight frequencies (crystal
oscillator: 75 kHz)
1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz
• Phase comparator
— Supports dead zone control
— Built-in unlock detection circuit
— Built-in deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 4
— I/O ports: 2
— Supports clock time base output
• Serial Data I/O
— Supports CCB format communication with the
system controller.
• Operating ranges
— Supply voltage: 2.5 to 3.6 V
— Operating temperature: –20 to +70°C
• Packages
—DIP22S/MFP20
Package Dimensions
unit: mm
3059-DIP22S
[LC72137]
unit: mm
3036B-MFP20
[LC72137M]
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO: DIP22S
SANYO: MFP20
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
70398RM(OT) No. 5743-1/23
1 page  
Block Diagram
LC72137, 72137M
No. 5743-5/23
5 Page 
LC72137, 72137M
Continued from preceding page.
No. Control block/data
DO pin control data
DOC0, DOC1, DOC2
Description
• Data that determines DO pin output
DOC2
0
0
0
0
1
1
1
1
DOC1
0
0
1
1
0
0
1
1
DOC0
0
1
0
1
0
1
0
1
DO pin state
Open
Low when the unlock state is detected
end-UC*1
Open
Open
The IO1 pin state*2
The IO2 pin state*2
Open
The open state is selected following a power-on reset.
Note: 1. end-UC: IF counter measurement completion check
(6)
Related data
UL0, UL1,
CTE,
IOC1, IOC2
Unlock detection data
UL0, UL1
(7)
Phase comparator
control data
DZ0, DZ1
(8)
When end-UC is set and an IF count is started (CTE = 0 → 1), the DO pin
automatically goes to the open state.
When the IF count measurement completes, the DO pin goes low and
the count completion check operation is enabled.
The DO pin goes to the open state due to serial data I/O (CE: high).
2. Goes to the open state if the IO pin itself is set to be an output port.
Caution: The DO pin always goes to the open state during the data input period (during the
period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin
control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal
DO serial data in synchronization with the CL pin signal during the data output period
(during the period when CE is high in the OUT mode) regardless of the values of
the DO pin control data (DOC0 to DOC2).
• Selects the phase error (øE) detection range for PLL lock discrimination.
When a phase error greater than the specified range occurs, the LC72136N determines
that the PLL is unlocked. (*: Don’t care.)
UL1 UL0
øE detection width
Detector output
0 0 Stopped
Open
0 10
øE is output directly
1 * ±6.67 µs
øE is extended by 1 to 2 ms
Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0.
• Phase comparator dead zone control data
DOC0,
DOC1,
DOC2
DZ1 DZ0
0 0 DZA
0 1 DZB
1 0 DZC
1 1 DZD
Dead zone mode
Dead zone width: DZA < DZB < DZC < DZD
(9) Clock time base
TBC
• An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1.
(The BO1 data will be ignored.)
Charge pump control data • Data that forcibly controls the charge pump output
DLC
DLC
Charge pump output
0 Normal operation
(10)
1 Forced low
Note: The LC72137 provides a technique for escaping from deadlock by setting Vtune to
VCC (deadlock clear circuit). This is used when the circuit is deadlocked due to the
VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V.
BO1
Continued on next page.
No. 5743-11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet LC72137M.PDF ] | |
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