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PDF LC72134M Data sheet ( Hoja de datos )
| Número de pieza | LC72134M | |
| Descripción | Dual PLL Frequency Synthesizer for FM Tuner Systems | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : EN5814
CMOS IC
LC72134M
Dual PLL Frequency Synthesizer
for FM Tuner Systems
Overview
The LC72134M is a dual PLL frequency synthesizer
product that integrates on a single chip both an AM/FM
audio broadcast reception PLL circuit (main PLL) and a
dedicated FM multiplex reception PLL circuit (sub PLL).
Since the main PLL circuit is equivalent to the
LC72135M, software developed for that product can be
used with this chip. The sub-PLL circuit can be controlled
independently.
Functions
• High-speed programmable divider
— FMINa (main): 10 to 160 MHz ... Pulse swallower
technique (With built-in divide-by-2 prescaler)
— FMINb (sub): 10 to 160 MHz ... Pulse swallower
technique (With built-in divide-by-2 prescaler)
— AMIN (main): 0.5 to 40 MHz ... Pulse swallower
and direct division techniques
• IF counter
— Two input pins provided: IFIN1 and IFIN2
— IFIN1: 0.4 to 25 MHz ... For AM and FM IF
counting
— IFIN2: 0.4 to 25 MHz ... For AM and FM IF
counting
• Reference frequency
— One of 12 reference frequencies can be selected
(using a 4.5 or 7.2 MHz crystal element)
1, 3, 5, 9, 10, 3.125, 6.25, 12.5*, 15*, 25*, 50*, or
100 kHz
*: Sub PLL reference frequencies
• Phase comparator
— Supports dead zone control.
— Built-in unlocked state detection circuit
— Built-in deadlock clear circuit
• An MOS transistor for an active low-pass filter is built
in.
• I/O ports
— Output-only ports: 4 pins
— I/O ports: 1 pin
— Input-only ports: 1 pin (function shared with the
IFIN2 pin)
— Supports the output of an 8-Hz clock time base
signal.
• CCB interface used for data I/O.
— The main PLL is compatible with the LC72135M.
— The sub PLL can be controlled at an independent
address.
• Operating ranges
— Supply voltage: 4.5 to 5.5 V
— Operating temperature: –40 to 85°C
• Package: MFP24S
Package Dimensions
unit: mm
3112-MFP24S
[LC72134M]
SANYO: MFP24S
This product supports the Sanyo-original CCB bus format.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
41098RM (OT) No. 5814-1/27
1 page  
Continued from preceding page.
Parameter
Output low-level voltage
Input high-level current
Input low-level current
Output off leakage current
High-level 3-state off leakage current
Low-level 3-state off leakage current
Input capacitance
Current drain
LC72134M
Symbol
Conditions
VOL1
VOL2
VOL3
VOL4
VOL5
IIH1
IIH2
IIH3
IIH4
IIH5
IIH6
IIH7
IIL1
IIL2
IIL3
IIL4
IIL5
IIL6
IIL7
IOFF1
IOFF2
IOFFH
IOFFL
CIN
IDD1
IDD2
IDD3
IDD4
PDa, PDb: IO = 1 mA
BO1: IO = 0.5 mA
BO1: IO = 1 mA
DO: IO = 1 mA
DO: IO = 5 mA
BO2 to BO4, IO2: IO = 1 mA
BO2 to BO4, IO2: IO = 5 mA
BO2 to BO4, IO2: IO = 8 mA
AOUTa, AOUTb: IO = 1 mA, AIN = 1.3 V
CE, DI, CL: VI = 6.5 V
IFIN2/I1: VI = VDD, L/I1 = 0
IO2: VI = 13 V
XIN: VI = VDD
FMINa, FMINb, AMIN: VI = VDD
IFIN1, IFIN2/I1: VI = VDD
AINa, AINb: VI = 6.5 V
CE, DI, CL: VI = 0 V
IFIN2/I1: VI = 0 V, L/I1 = 0
IO2: VI = 0 V
XIN: VI = 0 V
FMINa, FMINb, AMIN: VI = 0 V
IFIN1, IFIN2/I1: VI = 0 V
AINa, AINb: VI = 0 V
BO1 to BO4, AOUTa, AOUTb, IO2: VO = 13 V
DO: VO = 6.5 V
PDa, PDb: VO = VDD
PDa, PDb: VO = 0 V
FMINa, FMINb
VDD: Crystal = 7.2 MHz, fIN2 = 130 MHz
(FMINa operating), VIN2 = 40 mV rms
VDD: Crystal = 7.2 MHz, fIN2 = 130 MHz
(FMINa and FMINb operating),
VIN2 = 40 mV rms
VDD: PLL block stopped (PLL INHIBIT mode)
Crystal oscillator operating
(crystal frequency: 7.2 MHz)
VDD: PLL block stopped, crystal oscillator
stopped
min
2.0
4.0
8.0
2.0
4.0
8.0
Ratings
typ
0.01
0.01
6
5
8
0.5
max
1.0
0.5
1.0
0.2
1.0
0.2
1.0
1.6
0.5
5.0
5.0
5.0
11
22
44
200
5.0
5.0
5.0
11
22
44
200
5.0
5.0
200
200
10
Unit
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
nA
µA
µA
µA
µA
µA
µA
nA
µA
µA
nA
nA
pF
mA
16 mA
mA
10 µA
Pin Descriptions
Pin Pin No.
Type
XIN
XOUT
1
Xtal
24
Function
• Crystal oscillator element connections (4.5 or 7.2 MHz)
Equivalent circuit
• FMINa is selected when DVS in the serial data is set to 1.
FMINa
18
Main PLL
local oscillator
signal input
• Input frequency: 10 to 160 MHz
• The signal is passed through an internal divide-by-two prescaler and then input to
the swallow counter.
• The divisor can be set to a value in the range 272 to 65535. Since the internal
divide-by-two prescaler is used, the actual divisor will be twice the set value.
Continued on next page.
No. 5814-5/27
5 Page 
LC72134M
Continued from preceding page.
No. Control block/data
Function
• IF counter measurement start command data
CTE = 1: Starts the counter
CTE = 0: Resets the counter
• Determines the IF counter measurement time.
GT1
GT0 Measurement time
Wait time
IF counter control
data
CTE
GT0, GT1
00
01
10
11
4 ms
8
32
64
3 to 4 ms
3 to 4
7 to 8
7 to 8
3 * See the “Structure of the IF Counter” section for details.
• Specifies the IF counter input pin (IFIN1 or IFIN2/I1).
IF counter selection
data
LCTS
LCTS = 0: IFIN1
LCTS = 1: IFIN2/I1
L/I1 = 0: I1 (Input port)
L/I1 = 1: IFIN2 (IF counter 2)
L/I1
LCTS L/I1 IFIN2/I1 pin
IFIN1 pin
0 0 I1 (Input port)
IFIN1 (IF counter 1)
0 1 OFF (Pulled down)
1 0 I1 (Input port)
OFF (Pulled down)
1 1 IFIN2 (IF counter 2)
• Specifies input or output for the shared function I/O pin (IO2).
I/O port setup data
4 Data = 0: Input port
IOC2
Data = 1: Output port
• Determines the output state of the BO1 through BO4 and IO2 output ports.
Output port data
Data = 0: Open
5 BO1 to BO4
Data = 1: Low level
IO2
• The data is reset to 0, setting the pins to the open state, after a power on reset.
Related data
IFS
IOC2
Continued on next page.
No. 5814-11/27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet LC72134M.PDF ] | |
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