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PDF HE84G770 Data sheet ( Hoja de datos )
| Número de pieza | HE84G770 | |
| Descripción | 8-bit Micro-controller | |
| Fabricantes | King blillion Electronics | |
| Logotipo |  |
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King Billion Electronics Co., Ltd HE84G770
駿 億 電 子 股 份 有 限 公 司 wwHwE.D8a0ta0S0h4eeHt4SU.EcoRmIES
- Table of Contents -
1. General Description ___________________________________________________________________3
2. Features _____________________________________________________________________________3
3. Functional Block Diagram ______________________________________________________________4
4. Pin Description _______________________________________________________________________4
5. Pad Diagram _________________________________________________________________________7
6. ROM Map Configurations_____________________________________________________________11
7. External RAM/Flash Memory__________________________________________________________14
8. LCD Display RAM Map ______________________________________________________________15
9. LCD driver configurations_____________________________________________________________16
9.1. 16 Gray Scale LCD Display RAM Map ________________________________________________17
9.2. 4 Gray Scale LCD Display RAM Map _________________________________________________23
9.3. Black and White LCD Display RAM Map______________________________________________26
10. LCD Power Supply_________________________________________________________________29
11. Oscillators ________________________________________________________________________32
12. General Purpose I/O _______________________________________________________________33
13. Key Scan Circuit___________________________________________________________________35
14. Timer1 ___________________________________________________________________________37
15. Timer2 ___________________________________________________________________________38
16. Time Base ________________________________________________________________________39
17. Watch Dog Timer __________________________________________________________________39
18. Voice Output ______________________________________________________________________41
19. Low Voltage Detection/Reset _________________________________________________________46
20. Infrared output____________________________________________________________________47
21. Universal Asynchronous Receiver/Transmitter__________________________________________48
21.1. Interface Registers _________________________________________________________________49
21.2. Baud Rate Configuration Register ____________________________________________________49
21.3. Interrupt Enable, Identification Register ______________________________________________50
October 31, 2003
1
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
1 page  
King Billion Electronics Co., Ltd HE84G770
駿 億 電 子 股 份 有 限 公 司 wwHwE.D8a0ta0S0h4eeHt4SU.EcoRmIES
Pin Name I/O
Description
LCAP1A
O Charge Pump Capacitor Pin.
LVL5
P LCD Bias Voltage 5.
LVL4
P LCD Bias Voltage 4
LVL3
P LCD Bias Voltage 3
LVL2
P LCD Bias Voltage 2
LVL1
P LCD Bias Voltage 1.
LGS1
I Regulator Voltage Setting
LVREG
O
Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns pumped
to LVL5. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
VR12
I Charge Pump Input. The buffered output of the fine-adjusted VREG.
GND
P Power Ground Input.
VO O DAC Output.
DAO
O Alternate output of DAC.
OPIN
I Inverting input of OP Amp.
OPIP
I Non-inverting input of OP Amp.
OPO
O Output of OP Amp.
RSTP_N
I System Reset Input Pin. Level trigger, active low on this pin will put the chip in reset state.
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for RC
FXO,
O, type and ‘1’ for crystal type). For RC type oscillator, one resistor needs to be connected
FXI B between FXI and GND. For crystal oscillator, one crystal needs to be placed between FXI
and FXO. Please refer to application for details.
TSTP_P
I
Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for
improving ESD, please connect this point with zero Ohm resistor to GND.
External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base
SXO,
O, and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type
SXI I can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type and ‘1’ for crystal
oscillator.
VX
I
Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in
application circuit.
OLFR
O LCD frame signal for interfacing with LCD segment extender KDGS80.
OCCK
O LCD data load pin for interfacing with LCD segment extender KDGS80.
VDD
P
Positive power Input. A 0.1 µF decoupling capacitors should be placed as close to IC VDD
and GND pads as possible for best decoupling effect.
8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask
option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
PRTD[7..2]
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
PRTD[1]/SIN B input, ‘1’ must be outputted before reading the pin.
PRTD[0]/SOUT PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources.
PRTD[1] shares pad with UART Receiver SIN pin.
PRTD[0] shares pad with UART transmitter SOUT pin.
GND_PWM O Dedicated Ground for PWM output.
PWM
O
The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as one to
turn on PWM. Using VDD & PWM to drive output device.
IRO O The Infrared output.
4-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask
option MO_CPP[7..4] (‘1’ for push-pull and ‘0’ for open-drain).
PRTC[7..4]/
SCNI[3..0]
B
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, ‘1’ must be outputted before reading the pin.
PRTC[7..4] is shared with Key Scan Dedicated Input SCNI[3..0]. The Key Scan function
can be disabled by clearing MO_LCDKEY mask option to ‘0’.
VDD_RAM P Dedicated power input for RAM
CMSG[32..79] O COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to be
October 31, 2003
5
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
5 Page 
King Billion Electronics Co., Ltd HE84G770
駿 億 電 子 股 份 有 限 公 司 wwHwE.D8a0ta0S0h4eeHt4SU.EcoRmIES
6. ROM Map Configurations
The chip has built-in 1M bytes internal ROM including 512K bytes program ROM and 512K bytes data
ROM. In addition, address and data buses are provided to access External ROM. The MCU can access up
to 4 MB Program ROM and up to 16 MB Data space through external buses. The SEG[79..72],
SEG[71..44] pads are used as either data and address buses for external ROM or LCD segment driver
pads depending on the mask option MO_EXMEM. When the external ROM mask option is selected, the
MCU will retrieve the instructions and data from external ROM through the address and data buses and
the SEG[79..44] will not be LCD segment signals.
The bit 14 ~ 15 bit of 16-bit logical program address can be mapped to any one of 256 pages through
mapping registers PSA1, PSA2, PSA3. As logical page 0 can not be moved and is always physical page 0,
the PSA1 ~ PSA3 contain the physical page addresses of logical pages 1 ~ 3.
Logical Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Page Addr. A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A[15..14]
00
01
10
11
Logical Page
0
1
2
3
Physical Page Address Physical Address
0 00 A[13..0]
PSA1
PSA1+A[13..0]
PSA2
PSA2+A[13..0]
PSA3
PSA3+A[13..0]
Register Address Type
Bits Definition
Reset
PSA1 0x2C R/W A21 A20 A19 A18 A17 A16 A15 A14 0x01
PSA2 0x2D R/W A21 A20 A19 A18 A17 A16 A15 A14 0x02
PSA3 0x2E R/W A21 A20 A19 A18 A17 A16 A15 A14 0x03
October 31, 2003
11
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HE84G770.PDF ] | |
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