PDF IS61SF12832 Data sheet ( Hoja de datos )

Número de pieza	IS61SF12832
Descripción	(IS61SF12832 / IS61SF12836) 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM
Fabricantes	Integrated Silicon Solution
Logotipo
Hay una vista previa y un enlace de descarga de IS61SF12832 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas
No Preview Available ! IS61SF12832 IS61SF12836 128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ISSI® www.DataSheet4U.com APRIL 2001 FEATURES • Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 12 ns • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data inputs and control signals • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +3.3V +10%, –5% power supply • Power-down snooze mode DESCRIPTION The ISSI IS61SF12832 and IS61SF12836 are high-speed synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. It is organized as 131,072 words by 32 bits or 36 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 7.5 8 8.5 10 12 7.5 8 8.5 10 12 8.5 10 11 15 15 117 100 90 66 66 Units ns ns MHz ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 1 1 page IS61SF12832 IS61SF12836 TRUTH TABLE Operation Address Used CE Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L X X L L L X X H H X H X X H H X H ISSI ® www.DataSheet4U.com CE2 CE2 ADSP ADSC ADV WRITE OE DQ X X X L X X X High-Z X H L X X X X High-Z L X L X X X X High-Z X H H L X X X High-Z L X H L X X X High-Z H L L XXXXQ H L H L X Read X Q H L H L X Write X D X X H H L Read L Q X X H H L Read H High-Z X X X H L Read L Q X X X H L Read H High-Z X X H H L Write X D X X X H L Write X D X X H H H Read L Q X X H H H Read H High-Z X X X H H Read L Q X X X H H Read H High-Z X X H H H Write X D X X X H H Write X D PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW BWE HH HL HL HL LX BW1 X H L L X BW2 X H H L X BW3 X H H L X BW4 X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 5 5 Page IS61SF12832 IS61SF12836 ISSI ® www.DataSheet4U.com WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC(1) tKH(1) tKL(1) tAS(1) tSS(1) tWS(1) tDS(1) tCES(1) tAVS(1) tAH(1) tSH(1) tDH(1) tWH(1) tCEH(1) tAVH(1) Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Notes: 1. Tested with load in Figure 1. 7.5 Min. Max. 8.5 — 3— 3— 2— 2— 2— 2— 2— 2— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 8 Min. Max. 10 — 4— 4— 2— 2— 2— 2— 2— 2— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 8.5 Min. Max. 11 — 4.5 — 4.5 — 2— 2— 2— 2— 2— 2— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 10 Min. Max. 15 — 4.5 — 4.5 — 2— 2— 2— 2— 2— 2— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 12 Min. Max. 15 — 4.5 — 4.5 — 4— 4— 4— 4— 4— 4— 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 11 11 Page

Páginas	Total 16 Páginas
PDF Descargar	[ Datasheet IS61SF12832.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
IS61SF12832	(IS61SF12832 / IS61SF12836) 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM	Integrated Silicon Solution
IS61SF12836	(IS61SF12832 / IS61SF12836) 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM	Integrated Silicon Solution

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar