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Número de pieza STM6502
Descripción (STM6502 - STM6505) Dual push-button smart reset
Fabricantes ST Microelectronics 
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No Preview Available ! STM6502 Hoja de datos, Descripción, Manual

STM6502, STM6503
STM6504, STM6505
Dual push-button smart reset
Features
Operating voltage 1.0 V (active-low output
valid) to 5.5 V
Low supply current
Factory-programmable thresholds to monitor
VCC in the range of 1.575 to 4.625 V typ.
Open-drain, active-low reset output
Dual smart reset push-button inputs with
extended reset set up delay
Adjustable smart reset setup delay (tSRC):
by external capacitor or external resistor or
three-state logic
Power-on reset
Operating temperature:
industrial grade –40 °C to +85 °C
Package: TDFN-8L 2 x 2 x 0.75 mm,
0.5 mm pitch
RoHS compliant
TDFN-8L 2 x 2 mm
Applications
MP3 players
Portable navigation devices
Mobile phones
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Table 1. Device summary
Voltage inputs
Smart reset inputs
tSRC
Reset or Power
programming Good outputs
Part
number
Three-
VCC
VBAT
SR or
SR0
SR1
SRE
immediate,
independent
Ext.
SRC pin
state
input
TSR
RST
Package
BLD
STM6502(1)
✓✓
STM6503
✓✓
STM6504
STM6505
1. Contact local ST sales office for availability.
✓ ✓ TDFN-8L
✓✓
TDFN-8L
✓✓
TDFN-8L
✓ ✓ ✓ TDFN-8L
August 2009
Doc ID 16101 Rev 1
1/24
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1

1 page




STM6502 pdf
STM6502, STM6503, STM6504, STM6505
1 Description
Description
The smart reset devices provide a useful feature that ensures that inadvertent short reset
push-button closures do not cause system resets as the extended smart reset delay setup
periods are implemented. Hence, when valid smart reset input conditions and setup periods
are met, the RST output will generate a pulse which asserts the reset output for fixed
timeout period (tREC).
The typical application hookup shows that either the single smart reset input or the dual
reset inputs are also connected to the applications interrupt and control both the interrupt
pin and the hard reset functions. If the push-button is closed for a short time, the processor
is only interrupted. If the system still does not respond properly, holding the push-button(s)
and keeping it closed for the extended setup time (tSRC) causes a hard reset of the
processor. The smart reset feature helps significantly increase system stability and
eliminates the need for a dedicated reset button.
The STM65xx family of smart reset devices consists of low current microprocessor reset
circuits targeted for MP3 players, portable navigation, mobile phones and other portable
devices. The STM65xx devices feature single or dual smart reset inputs (SRx). The delayed
smart reset setup time (tSRC) options of 0 s, 2 s, 6 s and 10 s (all min.) are adjustable by an
external capacitor or resistor on the SRC pin or selectable by three-state logic, see Table 1.
The delayed setup period ignores short switch closures shorter than tSRC, thus preventing
unwanted resets.
The STM65xx devices have active-low open-drain reset (RST) output with power-on reset
function.
The reset output is also asserted when the monitored supply voltage VCC drops below the
specified threshold. The reset output remains asserted for the reset timeout period (tREC)
after the monitored supply voltage goes above the specified threshold.
STM6502 has two combined smart reset inputs (SR0 and SR1) with delayed smart reset
setup time (tSRC) programmed by either an external capacitor or resistor on the SRC pin
(device options).
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STM6503 is similar to STM6502, has two combined delayed smart reset inputs (SR0, SR1)
and three user-selectable delayed smart reset setup time (tSRC) options of 2 s, 6 s and 10 s
through a three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open,
tSRC = 6 s; when connected to VCC, tSRC = 10 s (all the times are minimum).
STM6504 has two independent smart reset inputs: SR0 provides the delayed smart reset
setup time (tSRC) function with three user-selectable tSRC options through a three-state TSR
input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when
connected to VCC, tSRC = 10 s (all the times are minimum), SRE provides instant reset. SRE
is edge trigger with a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge
after a valid reset period.
STM6505 has two combined delayed smart reset inputs (SR0, SR1) and provides
adjustable reset delay setup time via either an external capacitor or resistor connected to
the SRC pin. The RST output depends also on the VCC threshold. STM6505 also provides
independent low battery detect (BLD) output controlled by the secondary external input
voltage VBAT. The VBAT is monitored for low voltage and provides an indication on the
battery low detect output pin (BLD). VBAT threshold is 1.25 V, fixed, external resistor divider
to be used to set the actual battery voltage threshold. VBAT threshold hysteresis is 8 mV typ.
Doc ID 16101 Rev 1
5/24

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STM6502 arduino
STM6502, STM6503, STM6504, STM6505
Pin descriptions
3.5
Edge-triggered smart reset input (SRE) - STM6504 only
SRE is active-high, immediate and independent reset input, includes an edge trigger with
debounce delay on falling edge, tDEBOUNCE = 240 ms min. See timing diagram Figure 8.
Figure 8. STM6504 timing
t < tDEBOUNCE
=> counter reset
SR0
Independent
SRE
No debounce
RST
tREC
t < tSRC
tSRC
In this case, actual
tDEBOUNCE
RST low for > 240 ms
tREC
tREC
AM00328
3.6 Adjustable delay of smart reset input (SRC pin) - STM6502
and STM6505 only
This pin provides for controlling the setup time before the push-button action is validated by
reset output. It is connected to an external capacitor (CSRC), optionally external resistor
(RSRC), which is tied to ground for providing the desired value of setup time (tSRC).
The relation between tSRC and CSRC (RSRC) is given in Section 3.6.1: Optional smart reset
push-button setup delay times.
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Doc ID 16101 Rev 1
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