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PDF ISL9491A Data sheet ( Hoja de datos )

Número de pieza ISL9491A
Descripción LNB Power Supply and Control
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL9491A Hoja de datos, Descripción, Manual

Single Output LNB Supply Voltage Regulator for
Satellite Set-Top Box Applications
ISL9491, ISL9491A
Features
These devices are designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of single antenna
ports. Each device consists of a current-mode boost
converter and a low-noise linear regulator along with the
circuitry required for tone injection and pin controllable
interface. The device makes the total LNB supply design
simple, efficient and compact with low external
component count.
The current-mode boost converters provide the linear
regulator with input voltage that is set to the voltage at
the VOUT pin plus a minimal drop to insure minimum
power dissipation across the internal LDO. This maintains
constant voltage drop across the linear pass element
while permitting adequate voltage range for tone
injection.
The final regulated output voltage is available at the
cathode of the back diode to support the operation of an
antenna port for a single tuner. The outputs can be set to
various voltage level for the desired polarization
reception by means of the logic presented to the VSET0
and VSET1 pins. An EN pin is to be driven high to enable
the outputs for the PWM and linear combination; setting
EN low disables the output, forcing a shutdown mode.
The external modulation input (EXTM) can accept a tone
modulated DiSEqC command and transfer it
symmetrically to the output to meet DiSEqC 1.x protocol.
An external DiSEqC tank circuit can also be implemented
www.tDoatsauSphpeeotr4tUD.cioSmEqC 2.x.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL9491ERZ* 94 91ERZ -20 to +85 16 Ld QFN L16.4x4
ISL9491AERZ* 94 91AERZ -20 to +85 16 Ld QFN L16.4x4
*Add “-T” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3
termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
• Single Chip Power Solution
- Operation for 1-Tuner/1-Dish Applications
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with >92% Efficiency
- Pin Controllable Enable and Output
• 2.5V/3.3V/5V Logic Compatible
• FAULT Signal
• DIRECTV SWM Compliant
• VSET Pin to Toggle between Vertical and Horizontal
Polarizations
• External Tone Input
• Internal Overcurrent and Over-Temperature
Protection
• Pb-Free (ROHs Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top
Box
Pin Configuration
ISL9491, ISL9491A
(16 LD QFN)
TOP VIEW
16 15 14 13
VCC 1
CS 2
PGND 3
GATE 4
12 ILIMIT
11 TCAP
10 VSET1
9 VSET0
5 678
October 13, 2009
FN6531.0
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




ISL9491A pdf
ISL9491, ISL9491A
Absolute Maximum Ratings
VCC (Input Voltage) . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
VOUT, VSW . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 24V
BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
EN, VSET0/1, EXTM (Logic Control Pins) . . . . . -0.3V to 5.5V
All Pins Referenced to Ground
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 2, 3) . . . . . . . 47
9.5
Maximum Junction Temperature (Note 4) . . . . . . . +150°C
Maximum Storage Temperature Range . . . -40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
3. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside.
4. The device junction temperature should be kept below +150°C. Thermal shut-down circuitry turns off the device if junction
temperature exceeds +130°C typical.
Electrical Specifications
PARAMETER
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.
SYMBOL
TEST CONDITIONS
MIN TYP MAX
Operating Supply Voltage Range
ISL9491
8 12 14
ISL9491A
8 10 11
Supply Current (Ivcc current)
IIN EN = 1, Boost disconnected, and ext. 14.5V - 4 8
supply on VSW when VOUT = 13.3V,
No Load
UNDERVOLTAGE LOCKOUT
Stop Threshold
Input voltage falling from above 8V
- 4.4 -
Start Threshold
Input voltage rising from 0V
- 4.9 -
Output Voltage, ISL9491
www.DataSheet4U.com
VO EN = 1, VSET1 = 0, VSET0 = 0
EN = 1, VSET1 = 0, VSET0 = 1
EN = 1, VSET1 = 1, VSET0 = 0
12.8
17.7
13.8
13.3
18.3
14.3
13.6
18.7
14.6
EN = 1, VSET1 = 1, VSET0 = 1
19.4 20.0 20.4
Output Voltage, ISL9491A
VO EN = 1, VSET1 = 0, VSET0 = 0
EN = 1, VSET1 = 0, VSET0 = 1
10.5
14.5
11.0
15.0
11.3
15.3
EN = 1, VSET1 = 1, VSET0 = 0
11.5 12.0 12.3
EN = 1, VSET1 = 1, VSET0 = 1
15.5 16.0 16.3
Line Regulation
Load Regulation
DVO1,
DVO2
DVO1,
DVO2
VIN = 8V to 14V; VO = 13.30V
VIN = 8V to 14V; VO = 18.30V
IO = 0mA to 350mA, VOUT = 13.3V
IO = 0mA to 500mA, VOUT = 13.3V
(Note 4)
- 4 40
- 4 60
- 125 180
- 190 260
Output Overcurrent Threshold
Internal Regulator Overcurrent
Clamp
IOCT
IOCLMP
R at ILIMIT = 148k (Note 8)
Output Shorted to GND, RILIM = 0
270 350 435
860
UNITS
V
V
mA
V
V
V
V
V
V
V
V
V
V
mV
mV
mV
mV
mA
mA
5 FN6531.0
October 13, 2009

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ISL9491A arduino
ISL9491, ISL9491A
Functional Description
The ISL9491 or ISL9491A single output voltage regulator
makes an ideal choice for advanced satellite set-top box
and personal video recorder applications. The device
utilizes built-in DC/DC step-up converters, which operate
from a single supply source ranging from 8V to 14V and
generate the voltage needed to enable the linear
post-regulator to work with minimum dissipated power.
An undervoltage lockout circuit disables the device when
VCC drops below a fixed threshold (4.5V typical).
DiSEqC Encoding
The EXTM accepts an externally modulated tone
command and in turn modulates the VLNB symmetrically
to meet the DiSEqC 1.0 and DiSEqC 2.0 transmit
protocol. Burst coding of the tone can be accomplished
due to the fast response of the EXTM pin.
Linear Regulator
The output linear regulator is designed to source 500mA
continuous current and 750mA peak. The sink feature is
limited and thus requires a bleeder resistor of 3.3kΩ to
be connected at the VLNB to enable proper tone
modulation capability into capacitive loads as high as
0.22µF. In order to minimize the power dissipation, the
output voltage of the internal step-up converter is
adjusted to allow the linear regulator to work at a
minimum dropout of 1.2V typical (Load current =
500mA) between the VSW and VOUT pin. The VOUT pin
drives the anode of the back diode and the VSENSE pin
drives the cathode of the back diode. The VSENSE pin is
capable of withstanding a back voltage of 24V.
When the device is put in the shutdown mode
(EN = LOW), the PWM power block is disabled. When the
regulator blocks are active (EN = HIGH), the output can
be controlled by the VSET0 and VSET1 pins to be 13.3V,
14.3V, 18.3V or 20V (typical ISL9491) or 11V, 12V, 15V,
www.oDrat1aS6hVee(tt4yUp.iccoaml ISL9491A) for remote controlling of non-
DiSEqC LNBs.
A separate open-drain FAULT pin serves as an interrupt
and is driven low by undervoltage, overvoltage and linear
overcurrent and over-temperature faults.
Output Voltage Rise and Fall TimeTiming
The output voltage rise and fall times or soft-start time
can be set by an the external capacitor on the TCAP pin.
The output rise and fall times are given by Equation 1:
C
=
-2---2---0----t--r--i--s--e-
ΔV
(EQ. 1)
Where C is the TCAP value in nF, trise the required
transition time in ms and ΔV is the differential transition
voltage from low output voltage range to the high output
range in Volts.
Too large a value of TCAP prevents the output from rising
to the nominal value, within a reasonable time. Too small
a value of the TCAP can cause high peak currents in the
boost circuit. Figures 4 and 5 show the output voltage
rise time for TCAP value of 0.22µF and 0.44µF as 13.6ms
and 32ms which according to Equation 1 should be
13.3ms and 26.6ms. The difference between measured
and calculated values is due to capacitor tolerance of ±
20%. Since the output voltage uses TCAP voltage as a
reference, it is recommended to use a 10kΩ resistor in
series to filter out some of the switching noise from
injecting on this pin.
Dynamic and Static Current Limiting
When the LDO current exceeds the preset overcurrent
threshold set by means of a resistor from the ILIMIT pin
to GND for a period of 50ms, the device enters a
tON = 50ms/tOFF = 900ms routine. This type of current
limiting is also called “Dynamic Current Limiting”, which
is used extensively on other Intersil LNB controllers. A
linear overcurrent will drive the FAULT pin low during the
tOFF = 900ms period. This operation continues until the
fault is removed. Upon removal of the fault, the device
returns to normal operation after a successful soft-start
cycle. Figure 14 shows the output current and voltage
waveforms with an ILIMIT resistor of 148kΩ and a load
current of 350mA. It can be seen that under this loading
condition, the chip stays powered up and sources load
current for 50ms and turns-off for approximately 900ms.
The output voltage ramps up to programmed output
voltage during the on time.This cycle repeats itself until
load current is reduced below the current limit value of
350mA. Equation 2 shows the relationship between
ILIMIT resistor and load current:
ILIMIT
=
52,
000
×
---------α-----------
RILIMIT
(EQ. 2)
ILIMIT is the programmed load current in mA before the
chip goes into current limit where RILIMIT is in kΩ .
Alpha (α) is a gain term which is shown in Figure 19 and
has a value of one at 350mA. It is a good design practice
to use a 1% tolerance resistor and allow for at least 20%
higher margin on the maximum load current when
calculating the RILIMIT resistor value.
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
100 150 200 250 300 350 400 450 500 550
ILIMIT (mA)
FIGURE 19. ALPHA CONSTANT
Figure 15 shows the output current and voltage for
RILIMIT =148kΩ when the output voltage is shorted to
GND. Under this condition, the chip still exhibits the
50ms on and 900ms off pulse to minimize power
dissipation, however, current gets internally clamped to
approximately 750mA. The output voltage stays at 0V
11 FN6531.0
October 13, 2009

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