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ispClock5406D の電気的特性と機能

ispClock5406DのメーカーはLattice Semiconductorです、この部品の機能は「Zero Delay And Fan-Out Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispClock5406D
部品説明 Zero Delay And Fan-Out Buffer
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispClock5406D Datasheet, ispClock5406D PDF,ピン配置, 機能
ispClock5400D Family
In-System Programmable, Ultra-Low Jitter
Zero Delay and Fan-Out Buffer, Differential
November 2009
Preliminary Data Sheet DS1025
Features
CleanClock™ PLL
Ultra Low Period Jitter 2.5ps
Ultra Low Phase Jitter 6.5ps
Fully Integrated High-Performance PLL
• Programmable lock detect
• Four output dividers
• Programmable on-chip loop filter
• Compatible with Spread Spectrum clocks
• Internal/external feedback
Flexible Clock Reference and External
Feedback Inputs
• Programmable differential input reference/feed-
back standards
- LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
• Programmable termination
• Clock A/B selection multiplexer
FlexiClock™ I/O
40 MHz to 400 MHz Input/Output Operation
Dual Programmable Skew Per Output
• Programmable phase adjustment
- 16 settings; minimum step size 156 ps
- Up to +/- 9.4 ns skew range
- Coarse and fine adjustment modes
• Programmable time delay adjustment
www.DataSheet4U-.c1o6msettings; 18 ps
Dynamic Skew Control Through I2C
Low Output-to-Output Skew (<100ps)
Up to 10 Programmable Fan-out Buffers
• Programmable differential output standards and
individual enable controls
- LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
All I/Os are Hot Socket Compliant
Operating Modes
• Fan-out buffer with programmable output skew
control
• Zero delay buffer with dual programmable skew
controls
Dynamic Reconfiguration through I2C
Full JTAG Boundary Scan Test In-System
Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0° to 70°C) and Industrial (-40°
to 85°C) Temperature Ranges
48-Pin and 64-pin QFNS Packages
Applications
• Low-cost clock source for SERDES
• ATCA, MicroTCA, AMC, PCI Express
• Differential Clock Distribution
• Generic Source Synchronous Clock
Management
• Zero-delay clock buffer
ispClock5400D Family Functional Diagram
I2C
Interface
REFA
REFB
REFSEL
0
1
JTAG
FBK
*Available only in PLL mode.
PLL_BYPASS
Phase
Freq.
Detect
CleanClock PLL
Loop
Filter
VCO
Output
V-Dividers
÷2
0 ÷4
1 ÷8
÷16
Phase Skew
Control
Output
Routing
Matrix
FlexiClock Output Block
Phase
Skew
Control*
Time
Skew
Control T
Differential
Output
Drivers
+
+
+
+
+
+
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1025_01.2

1 Page





ispClock5406D pdf, ピン配列
Lattice Semiconductor
ispClock5400D Family Data Sheet
Figure 2-1. ispClock5410D Functional Block Diagram
REFA
REFB
VTT_REFA
VTT_REFB
VTT_FBK
LOCK
REFSEL
LOCK
DETECT
RESET
0
1
PHASE
LOOP
DETECT
FILTER
VCO
PLL_BYPASS
OUTPUT
V-DIVIDERS
÷2
0
÷4
1
÷8
÷16
OUTPUT ROUTING
MATRIX
FBK
USER 0
USER 1
USER 2
USER 3
I2C
Control/
Status
USER
PROGRAMMABLE
CONTROL/
STATUS
OE
Phase Skew
Time Skew
Output Routing
JTAG INTERFACE
TDI TMS TCK TDO
PHASE
SKEW
CONTROL
Figure 2-2. ispClock5406D Functional Block Diagram
REFA
REFB
VTT_REFA
VTT_REFB
VTT_FBK
LOCK
REFSEL
LOCK
DETECT
RESET
0
1
PHASE
LOOP
DETECT
FILTER
VCO
PLL_BYPASS
OUTPUT
V-DIVIDERS
÷2
0
÷4
1
÷8
÷16
OUTPUT ROUTING
MATRIX
www.DataSheet4U.com
FBK
USER 0
USER 1
USER 2
USER 3
USER
PROGRAMMABLE
CONTROL/
STATUS
I2 C
Control/
Status
OE
Phase Skew
Time Skew
Output Routing
JTAG INTERFACE
PHASE
SKEW
CONTROL
TDI TMS TCK TDO
PHASE
TIME
SKEW
SKEW OUTPUT
CONTROL CONTROL DRIVERS
BANK_0
BANK_1
BANK_2
BANK_3
BANK_4
BANK_5
BANK_6
BANK_7
BANK_8
BANK_9
PHASE
TIME
SKEW
SKEW OUTPUT
CONTROL CONTROL DRIVERS
BANK_0
BANK_1
BANK_2
BANK_3
BANK_4
BANK_5
2-3


3Pages


ispClock5406D 電子部品, 半導体
Lattice Semiconductor
ispClock5400D Family Data Sheet
Differential Input Characteristics (Applicable to REFA, REFB, FBK)
Symbol
Parameter
Conditions
VICM
VTHD
VIX
Common Mode Input Voltage - LVDS
Differential Input Threshold - LVDS
100mV < VICM < 300mV
300mV <VICM < 2.35V
Input Pair Differential Crosspoint Voltage
SSTL15, SSTL18, HSTL, eHSTL,
LVPECL, HCSL
Min.
0.1
±100
±50
0.3
Typ.
Max.
2.35
2.35
Units
V
mV
mV
V
Output Electrical Characteristics – LVDS
Symbol
VOH
VOL
VOD
VOD
VOS
VOS
Parameter
Output High Voltage
Output Low Voltage
Output Voltage Differential
Change in VOD Between H and L
Output Voltage Offset
Change in VOD Between H and L
ISA Output Short Circuit Current
ISAB Output Short Circuit Current
DCCKOUT Output Clock Duty Cycle
DC-ERROR Error in Duty Cycle1
tRF Rise and Fall Time1
1. Measured at fOUT = 400 MHz.
Conditions
RT = 100
RT = 100
RT = 100
Common Mode Output Voltage
VOD = 0V, Outputs Shorted to
GND, LVDS25
VOD = 0V, Outputs Shorted to
GND, LVDS33
VOD = 0V, Outputs Shorted to
Each Other
LVDS25 (Figure 2-3)
LVDS33 (Figure 2-3)
LVDS25 (Figure 2-3)
LVDS33 (Figure 2-3)
Min.
0.9
250
1.1
48
-50
-65
250
260
Typ.
1.375
1.03
400
1.2
Max.
1.6
450
50
1.375
50
24
35
5
52
50
65
550
400
www.DaOtauShtepet4uUt.coEmlectrical Characteristics – Differential LVPECL
Symbol
Parameter
VOH Output High Voltage1
VOL Output Low Voltage1
VOD Output Voltage Differential
DCCKOUT Output Clock Duty Cycle2
tRF Rise and Fall Time2
1. 100differential termination.
2. Measured at fOUT = 400 MHz.
Conditions
VCCO = 3.0V to 3.6V
VCCO = 3.3V
VCCO = 3.0V to 3.6V
VCCO = 3.3V
Figure 2-3
Figure 2-3
Min.
VCCO - 1.1
2.20
VCCO - 1.86
1.44
0.6
47
300
Typ.
Max.
VCCO - 0.88
2.42
VCCO - 1.62
1.68
1
53
400
Units
V
V
mV
mV
V
mV
mA
mA
mA
%
ps
ps
ps
ps
Units
V
V
V
V
V
%
ps
2-6

6 Page



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部品番号部品説明メーカ
ispClock5406D

Zero Delay And Fan-Out Buffer

Lattice Semiconductor
Lattice Semiconductor


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