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Número de pieza | ISPCLOCK5304S | |
Descripción | In-System Programmable Zero-Delay | |
Fabricantes | Lattice Semiconductor | |
Logotipo | ||
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No Preview Available ! ispClock™5300S Family
In-System Programmable, Zero-Delay
Universal Fan-Out Buffer, Single-Ended
October 2007
Preliminary Data Sheet DS1010
Features
■ Four Operating Configurations
• Zero delay buffer
• Zero delay and non-zero delay buffer
• Dual non-zero delay buffer
• Non-zero delay buffer with output divider
■ 8MHz to 267MHz Input/Output Operation
■ Low Output to Output Skew (<100ps)
■ Low Jitter Peak-to-Peak (< 70 ps)
■ Up to 20 Programmable Fan-out Buffers
• Programmable single-ended output standards
and individual enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
• Programmable lock detect
• Three “Power of 2” output dividers (5-bit)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
• Internal/external feedback
■ Precision Programmable Phase Adjustment
www.DataSh(eSekt4eUw.co)mPer Output
• 8 settings; minimum step size 156ps
- Locked to VCO frequency
• Up to +/- 5ns skew range
• Coarse and fine adjustment modes
■ Up to Three Clock Frequency Domains
■ Flexible Clock Reference and External
Feedback Inputs
• Programmable single-ended or differential input
reference standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, Differential
SSTL
• Clock A/B selection multiplexer
• Programmable Feedback Standards
- LVTTL, LVCMOS, SSTL, HSTL
• Programmable termination
■ All Inputs and Outputs are Hot Socket
Compliant
■ Full JTAG Boundary Scan Test In-System
Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■ 48-pin and 64-pin TQFP Packages
■ Applications
• Circuit board common clock distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
ispClock5300S Family Functional Diagram
LOCK
PLL_ BYPASS
REFA /
REFP
REFB /
REFN
REFSEL
FBK
+
0
1
PHASE
FREQ.
DETECT
LOOP
FILTER
VCO
OUTPUT
DIVIDERS
1 V0
0 5-Bit
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT 1
V1
5-bit
V2
5-bit
OUTPUT
ROUTING
MATRIX
OUTPUT N
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1010_01.4
1 page Lattice Semiconductor
ispClock5300S Family Data Sheet
Absolute Maximum Ratings
ispClock5300S
Core Supply Voltage VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage VCCA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
JTAG Supply Voltage VCCJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Driver Supply Voltage VCCO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Output Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130°C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
Symbol
Parameter
Conditions
VCCD
VCCJ
VCCA
VCCXSLEW
TJOP
Core Supply Voltage
JTAG I/O Supply Voltage
Analog Supply Voltage
VCC Turn-on Ramp Rate
Operating Junction Temperature
All supply pins
Commercial
Industrial
Commercial
TA
Ambient Operating Temperature
Industrial
1. Device power dissipation may also limit maximum ambient operating temperature.
ispClock5300S
Min.
Max.
3.0 3.6
1.62 3.6
3.0 3.6
— 0.33
0 120
-40 130
0 701
-40 851
Units
V
V
V
V/µs
°C
°C
Recommended
www.DataSheet4U.com
Operating
Conditions
–
VCCO
vs.
Logic
Standard
Logic Standard
VCCO (V)
Min.
Typ.
Max.
VREF (V)
Min.
Typ.
Max.
Min.
VTT (V)
Typ.
Max.
LVTTL
3.0 3.3 3.6
—
—
—
—
—
—
LVCMOS 1.8V
1.71 1.8 1.89
—
—
—
—
—
—
LVCMOS 2.5V
2.375 2.5 2.625
—
—
—
—
—
—
LVCMOS 3.3V
3.0 3.3 3.6
—
—
—
—
—
—
SSTL1.8
1.71 1.8 1.89 0.84
SSTL2 Class 1
2.375 2.5 2.625 1.15
SSTL3 Class 1
3.0 3.3 3.6 1.30
HSTL Class 1
1.425 1.5 1.575 0.68
eHSTL Class 1
1.71 1.8 1.89 0.84
Note: ‘—’ denotes VREF or VTT not applicable to this logic standard
0.90
1.25
1.50
0.75
0.90
0.95
1.35
1.70
0.90
0.95
— 0.5 x VCCO —
VREF - 0.04 VREF VREF + 0.04
VREF - 0.05 VREF VREF + 0.05
— 0.5 x VCCO —
— 0.5 x VCCO —
5
5 Page Lattice Semiconductor
ispClock5300S Family Data Sheet
Performance Characteristics – PLL
Symbol
Parameter
Conditions
Min. Typ. Max.
Units
fREF, fFBK
Reference and feedback input
frequency range
8 267 MHz
tCLOCKHI,
tCLOCKLO
tRINP,
tFINP
fPFD
Reference and feedback input
clock HIGH and LOW times
Reference and feedback input
rise and fall times
Phase detector input frequency
range
Measured between 20% and 80%
levels
1.25
8
ns
5 ns
267 MHz
fVCO
VDIV
VCO operating frequency
Output divider range (Power of
2)
160 400 MHz
1 32
fOUT
Output frequency range1
Fine Skew Mode
Coarse Skew Mode
5 267 MHz
2.5 200 MHz
tJIT (cc)
Output adjacent-cycle jitter5
(1000 cycle sample)
fPFD ≥ 100MHz
70 ps (p-p)
tJIT (per)
Output period jitter5
(10000 cycle sample)
fPFD ≥ 100MHz
9 ps (RMS)
tJIT(φ)
Reference clock to output jitter5
(2000 cycle sample)
fPFD ≥ 100MHz
50 ps (RMS)
tφ Static phase offset4
PFD input frequency ≥100MHz3
-40
100 ps
tφDYN
Dynamic phase offset
100MHz, Spread Spectrum
Modulation index = 0.5%
28
ps
DCERR Output duty cycle error
tPDBYPASS
Reference clock to output
propagation delay
Output type LVCMOS 3.3V2
fOUT >100 MHz
V=1
47 53
6.5
%
ns
tPD_FOB
Reference to output propagation
delay in Non-Zero Delay Buffer V=1
Mode
2.5 3.5
5
ns
www.DattDaESLhAeYet4U.cRionmetefernreanl cfeeetdoboauctkpmutoddeela3 y with V=1
500 ps
tLOCK
PLL lock time
From Power-up event
From RESET event
150 µs
15 µs
tRELOCK PLL relock time
To same reference frequency
To different frequency
15 µs
150 µs
PSR
Power supply rejection, period
jitter vs. power supply noise
fIN = fOUT = 100MHz
VCCA = VCCD = VCCO modulated with
100kHz sinusoidal stimulus
0.05
ps(RMS)
mV(p-p)
1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design).
2. See Figures 6 and 7 for output loads.
3. Input and outputs LVCMOS mode
4. Inserted feedback loop delay < 7ns
5. Measured with fOUT = 100MHz, fVCO = 400MHz, input and output interface set to LVCMOS.
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet ISPCLOCK5304S.PDF ] |
Número de pieza | Descripción | Fabricantes |
ISPCLOCK5304S | In-System Programmable Zero-Delay | Lattice Semiconductor |
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