PDF ISPCLOCK5600A Data sheet ( Hoja de datos )

Número de pieza	ISPCLOCK5600A
Descripción	Clock Generator
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispClock™5600A Family In-System Programmable, Enhanced Zero-Delay Clock Generator with Universal Fan-Out Buffer June 2008 Data Sheet DS1019 Features ■ 8MHz to 400MHz Input/Output Operation ■ Low Output to Output Skew (<50ps) ■ Low Jitter Peak-to-Peak ■ Up to 20 Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL • Programmable output impedance - 40 to 70Ω in 5Ω increments • Programmable slew rate • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V ■ Fully Integrated High-Performance PLL • Programmable lock detect • Multiply and divide ratio controlled by - Input divider (1 to 40) - Feedback divider (1 to 40) - Five output dividers (2 to 80) • Programmable on-chip loop ﬁlter • Compatible with spread spectrum clocks ■ Precision Programmable Phase Adjustment (Skew) Per Output • 16 settings; minimum step size 156ps - Locked to VCO frequency www.DataShe•et4UUp.ctoom+/- 12ns skew range • Coarse and ﬁne adjustment modes ■ Up to Five Clock Frequency Domains ■ Flexible Clock Reference and External Feedback Inputs • Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, SSTL • Clock A/B selection multiplexer • Feedback A/B selection multiplexer • Programmable termination ■ All Inputs and Outputs are Hot Socket Compliant ■ Four User-programmable Proﬁles Stored in E2CMOS® Memory • Supports both test and multiple operating conﬁgurations ■ Full JTAG Boundary Scan Test In-System Programming Support ■ Exceptional Power Supply Noise Immunity ■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges ■ 100-pin and 48-pin TQFP Packages ■ Applications • Circuit board common clock generation and distribution • PLL-based frequency generation • High fan-out clock buffer • Zero-delay clock buffer Product Family Block Diagram LOCK DETECT M * PHASE/ FREQUENCY FILTER DETECTOR N PLL CORE Internal/External Feedback Select JTAG INTERFACE & E2CMOS * MEMORY * Input Available only on ispClock5620A BYPASS MUX VCO OUTPUT DIVIDERS V0 V1 V2 V3 V4 Multiple Profile Management Logic 0123 INTERNAL FEEDBACK PATH SKEW OUTPUT CONTROL DRIVERS OUTPUT ROUTING MATRIX © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1019_01.4 1 page Lattice Semiconductor ispClock5600A Family Data Sheet E2CMOS Memory Write/Erase Characteristics Parameter Erase/Reprogram Cycles Conditions Min. 1000 Typ. — Max. — Units Performance Characteristics – Power Supply Symbol Parameter Conditions ICCD Core Supply Current3 ispClock5610A fVCO = 800MHz ispClock5620A fVCO = 800MHz ICCA Analog Supply Current3 fVCO = 800MHz VCCO = 1.8V1, LVCMOS, fOUT = 266MHz ICCO Output Driver Supply Current (per Bank) VCCO = 2.5V1, LVCMOS, fOUT = 266MHz VCCO = 3.3V1, LVCMOS, fOUT = 266MHz VCCO = 3.3V2, LVDS, fOUT = 400MHz VCCJ = 1.8V ICCJ JTAG I/O Supply Current (static) VCCJ = 2.5V VCCJ = 3.3V 1. Supply current consumed by each bank, both outputs active, 5pF load. 2. Supply current consumed by each bank, 100Ω, 5pf differential load. 3. All unused REFCLK and feedbacks connected to ground. Typ. 110 130 5.5 16 21 27 8 Max. 125 150 7 18 27 38 10 300 400 400 Units mA mA mA mA mA mA mA µA µA µA DC Electrical Characteristics – Single-ended Logic Logic Standard VIL (V) Min. Max. VIH (V) Min. Max. LVTTL/LVCMOS 3.3V -0.3 0.8 2 3.6 LVCMOS 1.8V -0.3 0.68 1.07 3.6 LVCMOS 2.5V -0.3 0.7 1.7 3.6 SSTL2 Class 1 -0.3 VREF - 0.18 VREF + 0.18 3.6 SSTL3 Class 1 www.DaHtaSSThLeeCt4laUs.cso1m -0.3 VREF - 0.2 VREF + 0.2 3.6 -0.3 VREF - 0.1 VREF + 0.1 3.6 eHSTL Class 1 -0.3 VREF - 0.1 VREF + 0.1 3.6 1. Speciﬁed for 40Ω internal series output termination. 2. Speciﬁed for ≈20Ω internal series output termination, fast slew rate setting. 3. For slower slew rate setting IOH, IOL = 8mA. VOL Max. (V) VOH Min. (V) 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.542 VCCO - 0.811 0.92 VCCO - 1.31 0.43 VCCO - 0.42 0.43 VCCO - 0.42 IOL (mA) 122, 3 122, 3 122, 3 7.6 8 8 8 IOH (mA) -122, 3 -122, 3 -122, 3 -7.6 -8 -8 -8 1-5 5 Page Lattice Semiconductor ispClock5600A Family Data Sheet Programmable Input and Output Termination Characteristics Symbol Parameter RIN Input Resistance Conditions Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω setting Rout≈20Ω setting Rout≈40Ω setting Rout≈45Ω setting ROUT Output Resistance1 Rout≈50Ω setting Rout≈55Ω setting www.DataSheet4U.com Rout≈60Ω setting Rout≈65Ω setting Rout≈70Ω setting 1. Guaranteed by characterization. VCCO Voltage VCCO=3.3V VCCO=2.5V VCCO=1.8V VCCO=1.5V VCCO=3.3V VCCO=2.5V VCCO=1.8V VCCO=3.3V VCCO=2.5V VCCO=1.8V VCCO=3.3V VCCO=2.5V VCCO=1.8V VCCO=3.3V VCCO=2.5V VCCO=1.8V VCCO=3.3V VCCO=2.5V VCCO=1.8V VCCO=3.3V VCCO=2.5V VCCO=1.8V VCCO=3.3V VCCO=2.5V VCCO=1.8V Min. 36 40.5 45 49.5 54 59 61 — — — — -9% -11% -13% -10% -12% -14% -8% -9% -13% -9% -11% -13% -8% -9% -14% -8% -9% -13% -9% -10% -12% Typ. — — — — — — — 15 15 16 14 40 40 41 45 45 48 50 50 54 55 55 59 59 59 63 65 64 69 72 70 74 Max. 44 49.5 55 60.5 66 71.5 77 — — — — 9% 11% 13% 10% 12% 14% 8% 9% 13% 9% 11% 13% 8% 9% 14% 8% 9% 13% 9% 10% 12% Units Ω Ω 1-11 11 Page

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