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PDF LM5060Q1 Data sheet ( Hoja de datos )
| Número de pieza | LM5060Q1 | |
| Descripción | High-Side Protection Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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LM5060Q1
November 3, 2009
High-Side Protection Controller with Low Quiescent
Current
General Description
The LM5060 high-side protection controller provides intelli-
gent control of a high-side N-Channel MOSFET during normal
on/off transitions and fault conditions. In-rush current is con-
trolled by the nearly constant rise time of the output voltage.
A power good output indicates when the output voltage reach-
es the input voltage and the MOSFET is fully on. Input Under-
Voltage Lock-Out, with hysteresis, is provided as well as
programmable input Over-Voltage Protection. An enable in-
put provides remote On / Off control. The programmable
Under-Voltage Lock-Out input can be used as second enable
input for safety redundancy. A single capacitor programs the
initial start-up VGS fault detection delay time, the transition
VDS fault detection delay time, and the continuous Over-Cur-
rent VDS fault detection delay time. When a detected fault
condition persists longer than the allowed fault delay time, the
MOSFET is latched off until either the Enable input or the Un-
der-Voltage Lock-Out input is toggled low and then high.
Features
■ Automotive grade / AEC Q-100
■ Wide operating input voltage range: +5.5V to +65V
■ Less than 15 µA quiescent current in disabled mode
■ Controlled output rise time for safe connection of
capacitive loads
■ Charge pump gate driver for external N-Channel MOSFET
■ Adjustable Under-Voltage Lock-Out (UVLO) with
hysteresis
■ UVLO serves as second enable input for systems
requiring safety redundancy
■ Programmable fault detection delay time
■ MOSFET latched off after load fault is detected
■ Active low open drain POWER GOOD (nPGD) output
■ Adjustable input Over-Voltage Protection (OVP)
■ Immediate restart after Over-Voltage shutdown
Applications
■ Automotive Body Electronics
■ Industrial Power Distribution and Control
Package
■ 10-Lead MINI-SOIC
Typical Application
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© 2009 National Semiconductor Corporation 301042
30104201
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1 page  
Symbol
Parameter
Conditions
VGATE
Gate output voltage in normal
operation
GATE - VIN Voltage
GATE Pin Open
VGATE-TH
VGS Status Comparator Threshold
voltage
GATE - OUT threshold voltage for TIMER
voltage reset and TIMER current change
VGATE-CLAMP
Zener Clamp between GATE Pin and
OUT Pin
IGATE-CLAMP = 0.1mA
Timer (TIMER Pin)
VTMRH
VTMRL
ITIMERH
ITIMERL
ITIMERR
tFAULT
Timer Fault Threshold
Timer Re-enable Threshold
Timer Charge Current for VDS Fault
Timer Start-Up Charge Current
Timer Reset Discharge Current
Fault to GATE Low delay
TIMER Pin Voltage Rising
TIMER pin Voltage Falling
TIMER Charge current after Start-Up.
VGS = 6.5V
TIMER Charge current during Start-Up.
VGS = 3.5V
TIMER Pin = 1.5V
TIMER Pin > 2.0V
No load on GATE pin
Power Good (nPGD Pin)
PGDVOL
PGDIOH
Output low voltage
Off leakage current
ISINK = 2 mA
VnPGD = 10V
Min. Typ. Max. Units
10 12 14 V
3.50 5 6.50 V
- 16.8 -
V
- 2.0 -
- 0.30 -
V
V
8.5 11 13.0 µA
4.0 6 7.0 µA
4.4 6 8.2 mA
- 5 - µs
- 80 205 mV
- 0.02 1.00 µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should
not be operated beyond such conditions. For guaranteed specifications and conditions, see the Electrical Characteristics table.
Note 2: The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Applicable standard is JESD-22–A114–C.
Note 3: Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Reflow temperature profiles are different for
lead-free and non-lead-free packages. Refer to the Packaging Data Book available from National Semiconductor, or : www.national.com/analog/packaging
Note 4: The GATE pin voltage is typically 12V above the VIN pin when the LM5060 is enabled. Therefore, the Absolute Maximum Rating for VIN (75V) applies
only when the LM5060 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 75V.
Note 5: The minimum voltage of -1V is allowed if the current is limited to below -25 mA. Also it is assumed that the negative voltage on the pins only occur during
reverse battery condition when a positive supply voltage (Vin) is not applied.
Note 6: The minimum voltage of -25V is allowed if the current is limited to below -25 mA. Also it is assumed that the negative voltage on the pins only occur during
reverse battery condition when a positive supply voltage (VIN) is not applied.
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5 www.national.com
5 Page 
FIGURE 1. Basic Application Circuit
30104222
Functional Description
The LM5060 is designed to drive an external high-side N-
channel MOSFET. Over-Current protection is implemented
by sensing the voltage drop across the MOSFET. When an
adjustable voltage drop threshold is exceeded, and an ad-
justable time period has elapsed, the MOSFET is disabled.
Over-Voltage Protection (OVP) and Under-Voltage Lock-Out
(UVLO) monitoring of the input line is also provided. A low
state on the enable pin will turn off the N-channel MOSFET
and switch the LM5060 into a very low quiescent current off
state. An active low power good output pin is provided to re-
port the status of the N-channel MOSFET. The waiting time
before the MOSFET is turned off after a fault condition is de-
tected can be adjusted with an external timer capacitor. Since
wwthwe.DLMat5a0S6h0eeuts4eUs.caocmonstant current source to charge the gate
of the external N-channel MOSFET, the output voltage rise
time can be adjusted by adding external gate capacitance.
This is useful when starting up into large capacitive loads.
POWER-UP SEQUENCE
The basic application circuit is shown in Figure 1 and a normal
start-up sequence is shown in Figure 2. Start-up of the
LM5060 is initiated when the EN pin is above the (ENTHH)
threshold (2.0V). At start-up, the timer capacitor is charged
with a 6 µA (typical) current source while the gate of the ex-
ternal N-channel MOSFET is charged through the GATE pin
by a 24 µA (typical) current source.
When the gate-to-source voltage (VGS) reaches the VGATE-
TH threshold (typically 5V) the VGS sequence ends, the timer
capacitor is quickly discharged to 0.3V, and begins charging
the timer capacitor with a11 µA current source.
The timer capacitor will charge until either the VDS Compara-
tor indicates that the drain-to-source voltage (VDS) has been
reduced to a nominal value (i.e. no fault) or the voltage on the
timer capacitor has reached the VTMRH threshold (i.e. fault).
The VDS Comparator monitors the voltage difference between
the SENSE pin and the OUT pin. The SENSE pin voltage is
user programmed to be lower than the input supply voltage
by selecting a suitable sense resistor value. When the OUT
pin voltage exceeds the voltage at the SENSE pin, the nPGD
pin is asserted low (i.e. no fault) and the timer capacitor is
discharged.
STATUS CONDITIONS
Output responses of the LM5060 to various input conditions
is shown in Table 1. The input parameters include Enable
(EN), Under-Voltage Lock-Out (UVLO), Over-Voltage Protec-
tion (OVP), input voltage (VIN), Start-Up Fault (VGS) and Run
Fault (VDS) conditions. The output responses are the VIN pin
current consumption, the GATE charge current, the TIMER
capacitor charge (or discharge) current, the GATE discharge
current if the timer capacitor voltage has reached the VTMRH
threshold (typically 2V), as well as the status of nPGD.
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| PDF Descargar | [ Datasheet LM5060Q1.PDF ] | |
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