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ISPMACH4000ZE の電気的特性と機能

ISPMACH4000ZEのメーカーはLattice Semiconductorです、この部品の機能は「1.8V In-System Programmable Ultra Low Power PLDs」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISPMACH4000ZE
部品説明 1.8V In-System Programmable Ultra Low Power PLDs
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ISPMACH4000ZE Datasheet, ISPMACH4000ZE PDF,ピン配置, 機能
ispMACH® 4000ZE Family
August 2008
1.8V In-System Programmable
Ultra Low Power PLDs
Data Sheet DS1022
Features
High Performance
• fMAX = 260MHz maximum operating frequency
• tPD = 4.4ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Ease of Design
• Flexible CPLD macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Ultra Low Power
• Standby current as low as 10µA typical
• 1.8V core; low dynamic power
• Operational down to 1.6V VCC
• Superior solution for power sensitive consumer
applications
• Per pin pull-up, pull-down or bus keeper
control*
Power Guard with multiple enable signals*
Broad Device Offering
• 32 to 256 macrocells
• Multiple temperature range support
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
• Space-saving packages
Easy System Integration
• Operation with 3.3V, 2.5V, 1.8V or 1.5V
LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing support
• Open-drain output option
• Programmable output slew rate
• 3.3V PCI compatible
• I/O pins with fast setup path
Input hysteresis*
• 1.8V core power supply
• IEEE 1149.1 boundary scan testable
• IEEE 1532 ISC compliant
• 1.8V In-System Programmable (ISP™) using
Boundary Scan Test Access Port (TAP)
• Pb-free package options (only)
On-chip user oscillator and timer*
www.DataSheet4U.com
Table 1. ispMACH 4000ZE Family Selection Guide
*New enhanced features over original ispMACH 4000Z
ispMACH 4032ZE
Macrocells
32
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
4.4
2.2
3.0
260
1.8V
Packages1 (I/O + Dedicated Inputs)
48-Pin TQFP (7 x 7mm)
32+4
64-Ball csBGA (5 x 5mm)
32+4
100-Pin TQFP (14 x 14mm)
144-Pin TQFP (20 x 20mm)
144-Ball csBGA (7 x 7mm)
1. Pb-free only.
ispMACH 4064ZE
64
4.7
2.5
3.2
241
1.8V
32+4
48+4
64+10
64+10
ispMACH 4128ZE
128
5.8
2.9
3.8
200
1.8V
64+10
96+4
96+4
ispMACH 4256ZE
256
5.8
2.9
3.8
200
1.8V
64+10
96+14
108+4
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1022_01.2

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ISPMACH4000ZE pdf, ピン配列
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can
support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-
patible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con-
nected to a VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
Architecture
There are a total of two GLBs in the ispMACH 4032ZE, increasing to 16 GLBs in the ispMACH 4256ZE. Each GLB
has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to
be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they
still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent
and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the asso-
ciated I/O cells in the I/O block.
Generic Logic Block
The ispMACH 4000ZE GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock
generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-
pled from macrocells through the ORP. Figure 2 illustrates the GLB.
Figure 2. Generic Logic Block
To GRP
www.DataSheet4U.com
36 Inputs
from GRP
Clock
Generator
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
To Product Term
Output Enable Sharing.
Also, To Input Enable of
Power Guard on I/Os
in the block.
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
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3Pages


ISPMACH4000ZE 電子部品, 半導体
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
Table 4. Product Term Expansion Capability
Expansion
Chains
Chain-0
Chain-1
Chain-2
Chain-3
Macrocells Associated with Expansion Chain
(with Wrap Around)
M0 M4 M8 M12 M0
M1 M5 M9 M13 M1
M2 M6 M10 M14 M2
M3 M7 M11 M15 M3
Max PT/
Macrocell
75
80
75
70
Every time the super cluster allocator is used, there is an incremental delay of tEXP. When the super cluster alloca-
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Power-up
Initialization
Shared PT Initialization
PT Initialization (optional)
PT Initialization/CE (optional)
www.DataSheet4U.com
From Logic Allocator
Delay
RP
D/T/L Q
From I/O Cell
To ORP
To GRP
CE
Single PT
Block CLK0
Block CLK1
Block CLK2
Block CLK3
PT Clock (optional)
Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
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共有リンク

Link :


部品番号部品説明メーカ
ISPMACH4000Z

3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

Lattice Semiconductor
Lattice Semiconductor
ISPMACH4000ZE

1.8V In-System Programmable Ultra Low Power PLDs

Lattice Semiconductor
Lattice Semiconductor


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