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PDF CY7C1371B Data sheet ( Hoja de datos )
| Número de pieza | CY7C1371B | |
| Descripción | (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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73B CY7C1371B
CY7C1373B
512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT
devices
• Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Registered inputs for flow-thru operation
• Byte Write capability
• Common I/O architecture
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10.0ns (for 83-MHz device)
• Single 3.3V –5% and +10% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP and 119 BGA packages
• Burst capability – linear or interleaved burst order
• JTAG boundary scan for BGA packaging version
• Automatic power down available using ZZ mode or CE
deselect
Functional Description
The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18
synchronous flow-thru burst SRAMs, respectively designed to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1371B/
CY7C1373B is equipped with the advanced No Bus Latency™
(NoBL) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write/Read transitions.The CY7C1371B/CY7C1373B is pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the byte Write Selects
(BWSa,b,c,d for CY7C1371B and BWSa,b for CY7C1373B) and
a Write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed Write circuitry. ZZ may be tied
to LOW if it is not used.
Synchronous Chip enables (CE1, CE2, CE3 on the TQFP, CE1
on the BGA) and an asynchronous Output enable (OE)
provide for easy bank selection and output three-state control.
In order to avoid bus contention, the output drivers are
synchronously three-stated during the data portion of a Write
sequence.
www.DaLtaoSgheicet4BUl.ococmk Diagram
CLK
ADV/LD
CY7C1371 CY7C1373
AX X = 18:0 X = 19:0
DQX X= a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
Ax
CEN
CE1
CE2
CE3
WE
BWSx
Mode
OE
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Control
and Write
Logic
117 MHz
7.5
250
20
D
CE
Data-In
Q
REG.
256K X 36/
512K X 18
Memory
Array
100 MHz
8.5
225
20
83 MHz
10.0
185
20
DQx
DPx
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05198 Rev. **
Revised February 4, 2002
1 page  
CY7C1371B
CY7C1373B
Pin Definitions
Name
A0
A1
A
BWSa
BWSb
BWSc
BWSd
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CLK
CE1
CE2
CE3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQa
I/O-
DQb
Synchronous
www.DatDaSQhceet4U.com
DQd
DPa
DPb
DPc
DPd
ZZ
MODE
I/O-
Synchronous
Input-
Asynchronous
Input Pin
VDD
VDDQ
VSS
TDO
Power Supply
I/O Power
Supply
Ground
JTAG serial output
Synchronous
Description
Address inputs used to select one of the 532,288/1,048,576 address locations. Sampled
at the rising edge of the CLK.
Byte Write Select inputs, active LOW. Qualified with WE to conduct Writes to the SRAM.
Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and
DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a Write sequence.
Advance/Load input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
Output enable, active LOW. Combined with the synchronous logic block inside the device
to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is
masked during the data portion of a Write sequence, during the first clock when emerging
from a deselected state and when the device has been deselected.
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
location specified by A[X] during the previous clock rise of the Read cycle. The direction of
the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the
pins can behave as outputs. When HIGH, DQa – DQd are placed in a three-state condition.
The outputs are automatically three-stated during the data portion of a Write sequence, during
the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE. DQ a, b, c and d are eight-bits wide.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].
During Write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is
controlled by BWSc, and DPd is controlled by BWSd. DP a, b, c and d are one-bit wide.
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE will default HIGH, to an interleaved burst order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of the system.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Document #: 38-05198 Rev. **
Page 5 of 26
5 Page 
TAP Controller State Diagram
1 TEST-LOGIC
RESET
0
TEST-LOGIC/
1
IDLE
www.DataSheet4U.com
SELECT
DR-SCAN
1
0
1
CAPTURE-DR
0
SHIFT-DR
0
1
EXIT1-DR
1
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
Note:
7. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C1371B
CY7C1373B
SELECT
IR-SCAN
0
1
CAPTURE-DR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
0
EXIT2-IR
1
UPDATE-IR
1
0
1
0
1
0
Document #: 38-05198 Rev. **
Page 11 of 26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet CY7C1371B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1371B | (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM | Cypress Semiconductor |
| CY7C1371C | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture |  Cypress |
| CY7C1371D | 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM | Cypress Semiconductor |
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