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PDF HD6412363 Data sheet ( Hoja de datos )
| Número de pieza | HD6412363 | |
| Descripción | 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Serie | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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REJ09B0050-0500
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2368 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2300 Series
www.DataSheet4U.com
H8S/2368F
H8S/2367F
H8S/2365
H8S/2364F
H8S/2363
H8S/2362F
H8S/2361F
H8S/2360F
HD64F2368
HD64F2367
HD6432365
HD64F2364
HD6412363
HD64F2362
HD64F2361
HD64F2360
Rev. 5.00
Revision Date: Aug 02, 2006
1 page  
Preface
The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing
Renesas Technology’s original architecture as their cores, and the peripheral functions required to
configure a system.
The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with direct memory access controller (DMAC) and data transfer controller
(DTC) bus masters, ROM and RAM, a 16-bit timer pulse unit (TPU), a programmable pulse
generator (PPG), 8-bit timers (TMR), a watchdog timer (WDT), serial communication interfaces
(SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as on-chip
peripheral modules required for system configuration. I2C bus interface 2 (IIC2) can also be
included as an optional interface.
A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM
and other kinds of memory.
A single-power flash memory (F-ZTAT) version is available for this LSI's ROM. This provides
flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of
mass production to full-scale mass production. This is particularly applicable to application
devices with specifications that will most probably change.
Note: F-ZTAT is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2368 Group in the
www.DataSheet4Ud.ceosmign of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2368 Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed
description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev. 5.00 Aug 02, 2006 page v of liv
5 Page 
Item
Page
19.1 Features
689
Figure 19.1 Block
690
Diagram of Flash Memory
Revision (See Manual for Details)
Description of "• Flash and memory emulation by RAM" deleted
Figure 19.1 amended
FLMCR1
FLMCR2
EBR1
EBR2
SYSCR
19.2 Mode Transitions
Table19.1 Differences
between Boot Mode and
User Program Mode
692
19.5 Register
Descriptions
697
Table19.1 amended
Programming control program*
Boot Mode
User Program Mode
Program/program-verify Erase/erase-verify/program/
program-verify
"• RAM emulation register (RAMER)" deleted
"RAM Emulation Register (RAMER)" description deleted
19.8.2 Software
Protection
19.11 Usage Notes
www.DataSheet4U.com
"Flash Memory Emulation in RAM" description deleted
710 Description amended
… SWE bit in FLMCR 1 to 0. When protection is in effect …
712 Description amended
… on-board programming mode, and programmer mode …
4. … during programming, erasing, or verifying.
5. Do not use ...
Rev. 5.00 Aug 02, 2006 page xi of liv
11 Page | ||
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