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CY14B256LA の電気的特性と機能

CY14B256LAのメーカーはCypress Semiconductorです、この部品の機能は「256 Kbit (32K x 8) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14B256LA
部品説明 256 Kbit (32K x 8) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14B256LA Datasheet, CY14B256LA PDF,ピン配置, 機能
CY14B256LA
256 Kbit (32K x 8) nvSRAM
Features
25 ns and 45 ns Access Times
Internally Organized as 32K x 8 (CY14B256LA)
Hands off Automatic STORE on Power Down with only a Small
Capacitor
STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
RECALL to SRAM Initiated by Software or Power Up
Infinite Read, Write, and Recall Cycles
1 Million STORE Cycles to QuantumTrap
20 year Data Retention
Single 3V +20% to -10% Operation
Industrial Temperature
44-Pin TSOP - II, 48-Pin SSOP, and 32-Pin SOIC Packages
Pb-free and RoHS Compliance
Functional Description
The Cypress CY14B256LA is a fast static RAM, with a nonvol-
atile element in each memory cell. The memory is organized as
32K bytes of 8 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power down. On power
up, data is restored to the SRAM (the RECALL operation) from
the nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
www.DataSheet4U.com
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54707 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 08, 2009
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CY14B256LA pdf, ピン配列
CY14B256LA
Pinouts
Figure 1. Pin Diagram - 44 Pin TSOP II/48 Pin SSOP
NC
NC[5]
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9 44 - TSOP II
10 (x8)
11
12 Top View
13 (not to scale)
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
NC[[43]]
NC
NC[2]
NC [1]
NC [1]
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
VCAP
A14
A13
A12
A11
A10
NC
NC
VCAP 1
48
NC 2
47
A14
A12
A7
3
4
5
46
45
44
A6 6
43
A5 7
42
NC 8
41
A4 9
NC 10
NC 11
48 - SSOP
(x8)
40
39
38
NC
VSS
NC
12
13
14
Top View
(not to scale)
37
36
35
NC
DQ0
A3
15
16
17
34
33
32
A2 18
31
A1 19
A0 20
30
29
DQ1 21
28
DQ2 22
27
NC 23
26
NC 24
25
VCC
NC
HSB
WE
A13
A8
A9
NC
A11
NC
NC
NC
VSS
NC
NC
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
Figure 2. Pin Diagram - 32-Pin SOIC
www.DataSheet4U.com
32 - SOIC
(x8)
Top View
(not to scale)
Notes
1. Address expansion for 1 Mbit. NC pin not connected to die
2. Address expansion for 2 Mbit. NC pin not connected to die.
3. Address expansion for 4 Mbit. NC pin not connected to die.
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
Document Number: 001-54707 Rev. *B
Page 3
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CY14B256LA 電子部品, 半導体
CY14B256LA
During any STORE operation, regardless of how it is initiated,
the CY14B256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the CY14B256LA remains disabled until the
HSB pin returns HIGH. Leave the HSB unconnected if it is not
used.
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven low by the HSB driver.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14B256LA Software
STORE cycle is initiated by executing sequential CE controlled
read cycles from six specific address locations in exact order.
During the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the nonvolatile
elements. After a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
www.6D.aRtaeSahdeeAt4dUd.rceosms 0x0FC0 Initiate STORE Cycle
Table 2. Mode Selection
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
CE
WE
OE
A14 - A0[6]
Mode
I/O Power
H
X
X
X
Not Selected Output High-Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x0E38
Read SRAM
Output Data
Active[7]
0x31C7
Read SRAM
Output Data
0x03E0
Read SRAM
Output Data
0x3C1F
Read SRAM
Output Data
0x303F
Read SRAM
Output Data
0x0B45
AutoStore
Output Data
Disable
Notes
6. While there are 15 address lines on the CY14B256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54707 Rev. *B
Page 6
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共有リンク

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部品番号部品説明メーカ
CY14B256L

256-Kbit (32K x 8) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14B256LA

256 Kbit (32K x 8) nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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