|
|
PDF IS46DR16320B Data sheet ( Hoja de datos )
| Número de pieza | IS46DR16320B | |
| Descripción | 512Mb DDR2 SDRAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS46DR16320B (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
|
No Preview Available !
IS43DR86400B, IS43/46DR16320B
512Mb (x8, x16) DDR2 SDRAM
FEATURES
PRELIMINARY INFORMATION
DECEMBER 2009
• Clock frequency up to 400MHz
• Posted CAS
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Additive Latency: 0, 1, 2, 3, 4 and 5
• Write Latency = Read Latency‐1
• Programmable Burst Sequence: Sequential or
Interleave
• Programmable Burst Length: 4 and 8
• Automatic and Controlled Precharge Command
• Power Down Mode
• Auto Refresh and Self Refresh
• Refresh Interval: 7.8 μs (8192 cycles/64 ms)
• OCD (Off‐Chip Driver Impedance Adjustment)
• ODT (On‐Die Termination)
• Weak Strength Data‐Output Driver Option
• Bidirectional differential Data Strobe (Single‐
ended data‐strobe is an optional feature)
• On‐Chip DLL aligns DQ and DQs transitions with
CK transitions
• Differential clock inputs CK and CK#
• VDD and VDDQ = 1.8V ± 0.1V
• PASR (Partial Array Self Refresh)
• SSTL_18 interface
• tRAS lockout supported
• Read Data Strobe supported (x8 only)
• Internal four bank operations with single pulsed
RAS
• Operating temperature:
Commercial (TA = 0°C to +70°C ; TC = 0°C to 85°C)
Industrial (TA = ‐40°C to +85°C; TC = ‐40°C to 95°C)
Automotive, A1 (TA = ‐40°C to +85°C; TC = ‐40°C to
95°C)
OPTIONS
• Configuration:
− 64Mx8 (16M x 8 x 4 banks)
− 32Mx16 (8M x 16 x 4 banks)
• Package:
− 60‐ball FBGA for x8
www.Da−taSh8e4e‐t4bUa.lcl oFmBGA for x16
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
64Mx8
A0‐A13
A0‐A9
BA0‐BA1
A10
32Mx16
A0‐A12
A0‐A9
BA0‐BA1
A10
Clock Cycle Timing
Speed Grade
CL‐tRCD‐tRP
tCK (CL=3)
tCK (CL=4)
tCK (CL=5)
‐5B
DDR2‐400B
3‐3‐3
5
5
5
‐37C
DDR2‐533C
4‐4‐4
5
3.75
3.75
‐3D
DDR2‐667D
5‐5‐5
5
3.75
3
‐25E
DDR2‐800E
6‐6‐6
5
3.75
3
‐25D
DDR2‐800D
5‐5‐5
5
3.75
2.5
Units
tCK
ns
ns
ns
tCK (CL=6) 5 3.75 3 2.5 2.5 ns
Frequency (max)
200
266
333
400
400 MHz
Note: The ‐5B device specification is shown for reference only.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
1
1 page  
IS43DR86400B, IS43/46DR16320B
Initialization Sequence after Power‐Up Diagram
tCH tCL
CK ~ ~ ~ ~ ~
tIS
CK# ~ ~ ~ ~ ~
ODT ~ ~ ~ ~ ~
~~
~~
~~
~~~
~~~
~~~
~
~
tIS
~
Command
~ ~ ~ ~ ~ ~NOP
PRE
ALL
EMRS
MRS
PRE
ALL
REF
~ REF
400ns
tRP
tMRD
tMRD
tRP
tRFC
Minimum 200 Cycles
~
tRFC
~ ~MRS
EMRS
EMRS
tMRD
Follow OCD
Flowchart
~
tOIT
Any
Com
DLL
Enable
DLL
Reset
OCD
Default
OCD Cal.
Mode Exit
Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, CAS# latency, DLL reset function, write recovery time (WR) are user defined
variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance,
additive CAS latency, ODT (On Die Termination), single‐ended strobe, and OCD (off chip driver impedance adjustment) are also user
defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register
(MR) or Extended Mode Registers EMR[1] and EMR[2] can be altered by re‐executing the MRS or EMRS Commands. Even if the user
chooses to modify only a subset of the MR, EMR[1], or EMR[2] variables, all variables within the addressed register must be
redefined when the MRS or EMRS commands are issued. The x16 option does not have A13, so all references to this address can be
ignored for this option.
MRS, EMRS and Reset DLL do not affect memory array contents, which mean re‐initialization including those can be executed at any
time after power‐up without affecting memory array contents.
DDR2 Mode Register (MR) Setting
www.DataSheet4U.com
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS# latency, burst
length, burst sequence, DLL reset, tWR, and active power down exit time to make DDR2 SDRAM useful for various applications. The
default value of the mode register is not defined, therefore the mode register must be written after power‐up for proper operation.
The mode register is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA0 and BA1, while controlling the state of address pins A0
– A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the mode register. The mode
register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register
contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in
the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ‐ A2
with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is
defined by A3; CAS latency is defined by A4 ‐ A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is
used for DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time tWR is defined by A9 ‐ A11. Refer to the
table for specific codes.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
5
5 Page 
IS43DR86400B, IS43/46DR16320B
Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is
effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and
WE# are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress
are not affected.
LOAD MODE (LM)
The mode registers are loaded via bank address and address inputs. The bank address balls determine which mode register will be
programmed. See “Mode Register (MR)” in the next section. The LM command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until tMRD is met.
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the bank
address inputs determines the bank, and the address inputs select the row. This row will remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same
bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the bank address inputs determine the
bank, and the address provided on address inputs A0–A9 selects the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL
feature, which allows a READ or WRITE command to be issued prior to tRCD(Min) by delaying the actual registration of the
READ/WRITE command to the internal device by AL clock cycles.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the bank select inputs selects the bank,
and the address provided on inputs A0–A9 selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if
wwawu.tDoa ptarSehcheeatr4gUe. ciso mnot selected, the row will remain open for subsequent accesses.
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to tRCD(MIN) by delaying the
actual registration of the READ/WRITE command to the internal device by AL clock cycles. Input data appearing on the DQ is written
to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data
transfer in the current bank and does not violate any other timing parameters. After a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if
there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the
precharge period will be determined by the last PRECHARGE command issued to the bank.
REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#‐before‐RAS# (CBR) REFRESH. All banks must
be in the idle mode prior to issuing a REFRESH command. This command is nonpersistent, so it must be issued each time a refresh is
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet IS46DR16320B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS46DR16320B | 512Mb DDR2 SDRAM | ISSI |
| IS46DR16320D | DDR2 DRAM | ISSI |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |