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IS43R16800A-6のメーカーはIntegrated Silicon Solutionです、この部品の機能は「8Meg x 16 128-MBIT DDR SDRAM」です。 |
部品番号 | IS43R16800A-6 |
| |
部品説明 | 8Meg x 16 128-MBIT DDR SDRAM | ||
メーカ | Integrated Silicon Solution | ||
ロゴ | |||
このページの下部にプレビューとIS43R16800A-6ダウンロード(pdfファイル)リンクがあります。 Total 30 pages
IS43R16800A-6
ISSI®
8Meg x 16
128-MBIT DDR SDRAM
FEATURES
• Clock Frequency: 166, 133 MHz
• Power supply (VDD and VDDQ): 2.5V
• SSTL 2 interface
• Four internal banks to hide row Pre-charge
and Active operations
• Commands and addresses register on positive
clock edges (CK)
• Bi-directional Data Strobe signal for data cap-
ture
• Differential clock inputs (CK and CK) for
two data accesses per clock cycle
• Data Mask feature for Writes supported
• DLL aligns data I/O and Data Strobe transitions
with clock inputs
• Half-strength and Matched drive strength
options
• Programmable burst length for Read and Write
operations
• Programmable CAS Latency (2, 2.5 clocks)
• Programmable burst sequence: sequential or
www.DataSihneteet4rUle.caovmed
• Burst concatenation and truncation supported
for maximum data throughput
• Auto Pre-charge option for each Read or Write
burst
• 4096 refresh cycles every 64ms
• Auto Refresh and Self Refresh Modes
• Pre-charge Power Down and Active Power
Down Modes
• Lead-free Availability
PRELIMINARY INFORMATION
APRIL 2006
DEVICE OVERVIEW
ISSI’s 128-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 134,217,728-bit memory
array is internally organized as four banks of 32M-bit to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is regis-
tered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CK. Commands are
registered on the positive edges of CK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
IS43R16800A-6
1M x16x8 Banks
VDD: 2.5V
VDDQ: 2.5V
66-pin TSOP-II
KEY TIMING PARAMETERS
Parameter
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
Clock Frequency
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
-6
DDR333
—
6
7.5
—
166
133
Unit
ns
ns
ns
MHz
MHz
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
1
1 Page IS43R16800A-6
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
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VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ15
CK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI®
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 CK
45 CK
44 CKE
43 NC
42 NC
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
WE
LDM, UDM
LDQS, UDQS
VDD
Vss
VDDQ
VssQ
NC
Write Enable
x16 Input/Output Mask
Data Strobe
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
3
3Pages IS43R16800A-6
ISSI®
CAPACITANCE CHARACTERISTICS (At TA = 0 to +25°C, VDD = VDDQ = 2.5V, f = 100 MHz)
Symbol
CIN1
CIN2
CIN3
COUT
Parameter
Input Capacitance: CK and CK
Input Capacitance: All other input pins
Data Mask Input/Output Capacitance: LDM/UDM
Data Input/Output Capacitance: DQs and LDQS/UDQS
Min.
2
2
3.8
3.8
Max.
3
3
4.8
4.8
Unit
pF
pF
pF
pF
DC ELECTRICAL CHARACTERISTICS (1,2,3,4,5) (VDD = 2.5V +/- 0.2V, TA = 0oC to +70oC)
Symbol Parameter
IDD0 Operating Current
IDD1 Operating Current
IDD2P
IDD2F
IDD2Q
Precharge Power-Down
Standby Current
Floating Idle
Standby Current
Quiet Idle
Standby Current
IDD3P
IDD3N
Active Power-Down
Standby Current
Active Standby Current
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IDD4R Operating Current
Burst Read
IDD4W Operating Current
Burst Write
IDD5 Auto Refresh Current
IDD6 Self Refresh Current
IDD7 Operating Current
Test Condition
One bank operation; Active-Precharge; DQ, DM and DQS
inputs change once per clock cycle; Address and Control
inputs change once per two clock cycles; tRC = tRC (min)
One bank operation; Active-Read-Precharge; BL = 4; CL = 2.5;
Address and Control inputs change once per clock cycle;
tRCDRD = 4 x tCK; tRC = tRC (min); IOUT = 0mA;
All banks Idle; CKE ≤ VIL
CKE ≥ VIH; CS ≥ VIH; DQ, DQS, DM = VREF
All banks idle; Address and control inputs change once per
clock cycle; CKE = High; CS = High (Deselect); VIN = VREF
for DQ, DQS, and DM; tCK = tCK (min)
One bank Active; CKE = Low; tCK = tCK (min)
One bank Active; CS = High; CKE = High; Address and
Control inputs change once per clock cycle; DQ, DQS, and
DM change twice per clock cycle; tRC = tRC (max);
One bank Active; CKE ≥ VIH; BL = 2; Address and Control inputs
change once per clock cycle; tCK = tCK (min); IOUT = 0mA;
CL = 2.5
One bank Active; BL = 2; Address and Control inputs change
once per clock cycle; DQ, DQS, DM change twice per clock
cycle; CKE ≥ VIH; CL = 2.5
tRC = tRFC (min); Input ≤ VIL or ≥ VIH
Input ≥ VDD-0.2V; Input ≤ 0.2V
Four bank interleaved Reads with Auto Precharge; BL = 4;
Address and Controls inputs change per Read, Write, or
Active command; one bank with tRC = tRC (min)
Notes:
1. Operating outside the “Absolute Maximum Ratings” may lead to temporary or permanent device failure.
2. Power up sequence describe in “Initialization” section.
3. All voltages are referenced to VSS.
4. IDD tested without DQ pins connected.
5. IDD values tested with tCK = tCK (min).
Unit
110 mA
140 mA
3 mA
35 mA
30 mA
20 mA
55 mA
205 mA
205 mA
200 mA
3 mA
350 mA
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
6 Page | |||
ページ | 合計 : 30 ページ | ||
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部品番号 | 部品説明 | メーカ |
IS43R16800A-6 | 8Meg x 16 128-MBIT DDR SDRAM | Integrated Silicon Solution |