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PDF IS43R16160A Data sheet ( Hoja de datos )
| Número de pieza | IS43R16160A | |
| Descripción | 16Meg x 16 256-MBIT DDR SDRAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS43R16160A
ISSI®
16Meg x 16
256-MBIT DDR SDRAM
FEATURES
• Clock Frequency: 200, 166 MHz
• Power supply (VDD and VDDQ)
DDR 333: 2.5V + 0.2V
DDR 400: 2.6V + 0.1V
• SSTL 2 interface
• Four internal banks to hide row Pre-charge
and Active operations
• Commands and addresses register on positive
clock edges (CK)
• Bi-directional Data Strobe signal for data cap-
ture
• Differential clock inputs (CK and CK) for
two data accesses per clock cycle
• Data Mask feature for Writes supported
• DLL aligns data I/O and Data Strobe transitions
with clock inputs
• Half-strength and Full-strength drive strength
options
• Programmable burst length for Read and Write
operations
•www.DataSPhereotg4Ura.cmommable CAS Latency (2, 2.5, or 3
clocks)
• Programmable burst sequence: sequential or
interleaved
• Burst concatenation and truncation supported
for maximum data throughput
• Auto Pre-charge option for each Read or Write
burst
• 8192 refresh cycles every 64ms
• Auto Refresh and Self Refresh Modes
• Pre-charge Power Down and Active Power
Down Modes
• Lead-free available
PRELIMINARY INFORMATION
NOVEMBER 2005
DEVICE OVERVIEW
ISSI’s 256-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 268,435,456-bit memory
array is internally organized as four banks of 64M-bit to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is regis-
tered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CK. Commands are
registered on the positive edges of CK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
KEY TIMING PARAMETERS
Parameter
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
Clock Frequency
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
-5 -6 Unit
DDR400 DDR333
5 6 ns
6 6 ns
7.5 7.5 ns
200 166 MHz
166 166 MHz
133 133 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
11/28/05
1
1 page  
IS43R16160A
ISSI®
Functional Description
■ Power-Up Sequence
The following sequence is required for POWER UP.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.
4. Precharge all banks.
5. Issue EMRS to enable DLL.(To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0
and “Low” to all of the rest address pins, A1~A11 and BA1)
6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is
required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command to initialize device operation.
Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it,
the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Power up Sequence & Auto Refresh(CBR)
CK, CK
Command
01 23 45 678
•• ••
2 Clock min.
2 Clock min.
precharge
ALL Banks
EMRS
MRS
DLL Reset
tRP
precharge
ALL Banks
1st Auto
Refresh
200 µS Power up
to 1st command
min. 200 Cycle
456 7 8
9 10 11 12 13 14 15 16 17 18 19
••
tRFC
••
••
2nd Auto
Refresh
••
tRFC
••
••
2 Clock min.
Mode
Register Set
Any
Command
8
www.DataSheet4U.com
Extended Mode Register Set (EMRS)
The extended mode register stores the data for enabling or disabling DLL. The default value of the extend-
ed mode register is not defined, therefore the extended mode register must be written after power up for en-
abling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and
high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A0 ~ A12 and BA1 in the same cycle as CS, RAS,
CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used
for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0
must be set to low for proper EMRS operation. A1 is used at EMRS to indicate I/O strength A1 = 0 full strength,
A1 = 1 half strength. Refer to the table for specific codes.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
11/28/05
5
5 Page 
IS43R16160A
ISSI®
Auto Precharge Operation
The Auto Precharge operation can be issued by having column address A10 high when a Read or Write
command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst
operation is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once tRAS(min) is satisfied.
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length = 4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tRAS(min)
tRP(min)
CK, CK
Command
ACT
NOP R/w AP NOP
NOP
NOP
NOP
BA
NOP
DQS
DQ
D0 D1 D2 D3
Begin Autoprecharge
Earliest Bank A reactivate
www.DataSheet4U.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
11/28/05
11
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