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BLD6G21LS-50 の電気的特性と機能

BLD6G21LS-50のメーカーはNXP Semiconductorsです、この部品の機能は「TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor」です。


製品の詳細 ( Datasheet PDF )

部品番号 BLD6G21LS-50
部品説明 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
メーカ NXP Semiconductors
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BLD6G21LS-50 Datasheet, BLD6G21LS-50 PDF,ピン配置, 機能
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty
transistor
Rev. 01 — 28 October 2009
Objective data sheet
1. Product profile
1.1 General description
The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution
using NXP’s state of the art GEN6 LDMOS technology. This device is perfectly suited for
TD-SCDMA base station applications at frequencies from 2010 MHz to 2025 MHz. The
main and peak device, input splitter and output combiner are integrated in a single
package. This package consists of one gate and drain lead and two extra leads of which
one is used for biasing the peak amplifier and the other is not connected. It only requires
the proper input/output match and bias setting as with a normal class-AB transistor.
Table 1. Typical performance
RF performance at Th = 25 °C.
Mode of operation
f
(MHz)
TD-SCDMA [1][2]
2010 to 2025
VDS PL(AV)
(V) (W)
28 8
Gp ηD ACPR
(dB) (%) (dBc)
13.5 42 23
[1] Test signal: 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF.
[2] IDq = 170 mA (main); VGS(amp)peak = 0 V.
PL(3dB)
(W)
50
CAUTION
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This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features
I Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz:
N Average output power = 8 W
N Power gain = 13.5 dB
N Efficiency = 42 %
I Fully optimized integrated Doherty concept:
N integrated asymmetrical power splitter at input
N integrated power combiner
N peak biasing down to 0 V
N low junction temperature
N high efficiency
I Integrated ESD protection

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BLD6G21LS-50 pdf, ピン配列
NXP Semiconductors
4. Block diagram
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
RF-input/bias main 2
main
amplifier
90
bias peak 5
90
1
peak
amplifier
RF-output/VDS
001aak932
Fig 1. Block diagram of BLD6G21L-50 and BLD6G21LS-50
5. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Valid for both main and peak device.
Symbol
Parameter
Conditions
VDS
VGS(amp)main
VGS(amp)peak
ID
Tstg
Tj
drain-source voltage
main amplifier gate-source voltage
peak amplifier gate-source voltage
drain current
storage temperature
junction temperature
Min Max Unit
- 65 V
0.5 +13 V
0.5 +13 V
- 10.2 A
65 +150 °C
- 200 °C
6. Thermal characteristics
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Table 5. Thermal characteristics
Symbol Parameter
Rth(j-case) thermal resistance from junction to case
Conditions
Typ
Tcase = 80 °C; PL = 8 W [1] 2.4
Unit
K/W
[1] When operated with a 6-carrier TD-SCDMA modulated signal with PAR = 10.8 dB at 0.01 % probability on
CCDF.
BLD6G21L-50_BLD6G21LS-50_1
Objective data sheet
Rev. 01 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
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3Pages


BLD6G21LS-50 電子部品, 半導体
NXP Semiconductors
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
16
Gp
(dB)
14
12
(3)
(2)
(1)
001aak936
60
ηD
(%)
40
20
001aak937
(3)
(2)
(1)
10
30 36 42 48
PL (dBm)
0
30 36 42 48
PL (dBm)
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
VGS(amp)peak = 0 V; δ = 10 %; tp = 100 µs on 1 ms period.
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
Fig 5. Power gain as a function of load power;
typical values
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
VGS(amp)peak = 0 V; δ = 10 %; tp = 100 µs on 1 ms period.
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
Fig 6. Drain efficiency as a function of load power;
typical values
www.DataSheet4U.com
50
RLin
(dB)
40
001aak938
30
20
(3)
(2)
10
(1)
0
30 36 42 48
PL (dBm)
VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C; δ = 10 %; tp = 100 µs on 1 ms period.
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
Fig 7. Input return loss as a function of load power; typical values
BLD6G21L-50_BLD6G21LS-50_1
Objective data sheet
Rev. 01 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
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部品番号部品説明メーカ
BLD6G21LS-50

TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor

NXP Semiconductors
NXP Semiconductors


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