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CP3SP33 の電気的特性と機能

CP3SP33のメーカーはNational Semiconductorです、この部品の機能は「Connectivity Processor」です。


製品の詳細 ( Datasheet PDF )

部品番号 CP3SP33
部品説明 Connectivity Processor
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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CP3SP33 Datasheet, CP3SP33 PDF,ピン配置, 機能
PRELIMINARY
September 2005
CP3SP33 Connectivity Processor with Cache, DSP, and
Bluetooth®, USB, and Dual CAN Interfaces
1.0 General Description
The CP3SP33 connectivity processor combines high per-
formance with the massive integration needed for embed-
ded Bluetooth applications. A powerful RISC core with 4K-
byte instruction cache and a Teak® DSP coprocessor pro-
vides high computing bandwidth, DMA-driven hardware
communications peripherals provide high I/O bandwidth,
and an external bus provides system expandability.
On-chip communications peripherals include: Bluetooth
Lower Link Controller, Universal Serial Bus (2.0) OTG node
and host controller, dual CAN, dual Microwire/Plus/SPI,
dual ACCESS.bus, quad UART, 10-bit A/D converter, and
telematics/audio codec. Additional on-chip peripherals in-
clude DMA controller, dual CVSD/PCM conversion module,
I2S and AAI digital audio bus interfaces, Timing and Watch-
dog Unit, dual Versatile Timer Unit, dual Multi-Function Tim-
er, and Multi-Input Wake-Up (MIWU) unit.
In addition to providing the features needed for the next gen-
eration of embedded Bluetooth products, the CP3SP33 is
backed up by the software resources that designers need
for rapid time-to-market, including an operating system,
Bluetooth protocol stack implementation, peripheral drivers,
reference designs, and an integrated development environ-
ment. Combined with an external program memory and a
Bluetooth radio transceiver such as National’s LMX5252,
the CP3SP33 provides a complete Bluetooth system solu-
tion.
National Semiconductor offers a complete and industry-
proven application development environment for CP3SP33
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth protocol stack, and applica-
tion examples.
Block Diagram
www.DataSheet4U.com
Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor. Teak is a registered trademark of ParthusCeva, Inc.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
©2005 National Semiconductor Corporation
www.national.com

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CP3SP33 pdf, ピン配列
3.0 Device Overview
The CP3SP33 connectivity processor is an advanced mi-
crocomputer with system timing, interrupt logic, instruction
cache, data memory, and I/O ports included on-chip, mak-
ing it well-suited to a wide range of embedded applications.
The block diagram on page 1 shows the major on-chip com-
ponents of the CP3SP33.
3.1 CR16CPLUS CPU CORE
The CP3SP33 contains a CR16CPlus CPU core. This core
improves upon the performance of previous CP3000 devic-
es by adding a 4-Kbyte instruction cache and doubling the
CPU core data bus bandwidth. The cache greatly reduces
instruction-fetch bandwidth on the 32-bit system bus, which
leaves more bus bandwidth available for DMA-based I/O.
The cache moves the average execution rate closer to the
peak rate of one instruction per clock cycle, especially when
executing from off-chip program memory. The DMA control-
ler provides efficient sharing of the CPU core bus between
the CPU and high-bandwidth peripherals such as wired and
wireless communication interfaces.
For information on the instruction set architecture, please
refer to the CR16C Programmer’s Reference Manual (doc-
ument number 424521772-101, which may be downloaded
from National’s web site at http://www.national.com).
3.2 TEAK DSP CORE
The Teak 16-bit fixed-point DSP core is designed for low-
power, high-speed digital signal processing applications, in-
cluding acoustic echo cancellation, noise reduction, and
MP3/WMA decoding. It features a four-bus, dual-MAC, en-
hanced Harvard architecture. The DSP has 24K bytes of
dedicated program RAM, 24K bytes of data RAM, and a 4K-
byte RAM shared with the CPU. The DSP has a bus master
interface to the 4K-byte shared RAM and an external mem-
ory bus. It also has a bus master interface to a shared audio
peripheral bus. The DSP is slave on the CPU peripheral
bus, for downloading software to the program RAM.
www.DataShTeheet4DUS.cPomhas its own DMA controller for I/O and memory ac-
cess.
3.3 AMBA BUS ARCHITECTURE
The CPU and DSP core buses implement AMBA-compati-
ble AHB high-performance 32-bit buses with bursting and
split transactions. The CPU peripheral bus and CPU/DSP
shared audio peripheral bus implement AMBA-compatible
32-bit APB buses. The CPU and DSP buses operate at in-
dependent rates up to 96 MHz. The APB buses operate at
a rate which is a factor of 1, 2, or 4 slower than the CPU
AHB bus.
3.4 EXTERNAL BUS INTERFACE UNIT
The External Bus Interface Unit (EBIU) provides program-
mable timing, memory type, base address, size, and bus
width (8, 16, or 32 bits) for three regions of up to 32M bytes.
An 8-level write buffer releases the bus master to continue
execution without waiting for write cycles to complete.
3.5 MEMORY
The CP3SP33 devices support a uniform linear address
space. Three types of on-chip memory occupy specific re-
gions within this address space, along with any external
memory:
„ 32K bytes of CPU RAM
„ 4K bytes of CPU/DSP shared RAM
„ 8K bytes of Bluetooth sequencer and data RAM
„ Up to 32M bytes of external memory
A non-volatile external program memory is used to store the
application program, Bluetooth protocol stack, and real-time
operating system.
The 32K bytes of CPU RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, de-
pending on the instruction executed by the CPU.
3.6 BLUETOOTH LLC
The integrated hardware Bluetooth Lower Link Controller
(LLC) complies to the Bluetooth Specification Version 1.2
and integrates the following functions:
„ 7K-byte dedicated Bluetooth data RAM
„ 1K-byte dedicated Bluetooth sequencer RAM
„ Support of all Bluetooth 1.2 packet types and extended
Synchronous Connection-Oriented (eSCO) links
„ Support for fast frequency hopping of 1600 hops/s
„ Access code correlation and slot timing recovery circuit
„ Power Management Control Logic
„ BlueRF-compatible interface (mode 2/3) to connect with
National’s LMX5252 and other RF transceiver chips
3.7 USB
The full-speed Universal Serial Bus (USB) node and host
controller is compatible with USB Specification 2.0 and USB
On-The-Go. It integrates the required USB transceiver, the
Serial Interface Engine (SIE), and USB endpoint FIFOs. A
total of seven endpoint pipes are supported: one bidirection-
al pipe for the mandatory control EP0 and an additional six
pipes for unidirectional endpoints to support USB interrupt,
bulk, and isochronous data transfers.
The on-chip USB transceiver features an integrated pullup
resistor on the D+ line to UVCC. This pullup resistor can be
switched in or out by the USB VBUS sense input (VBUS),
which eliminates the need for external components.
3.8 CAN INTERFACE
The two CAN modules support Full CAN 2.0B class, CAN
serial bus interfaces for applications that require a high-
speed (up to 1 Mbits per second) or a low-speed interface
with CAN bus master capability. The data transfer between
CAN and the CPU is established by 15 memory-mapped
message buffers, which can be individually configured as
receive or transmit buffers. An incoming message is filtered
by two masks, one for the first 14 message buffers and an-
other one for the 15th message buffer to provide a basic
CAN path. A priority decoder allows any buffer to have the
highest or lowest transmit priority. Remote transmission re-
quests can be processed automatically by automatic recon-
figuration to a receiver after transmission or by automated
3 www.national.com


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CP3SP33 電子部品, 半導体
In addition, the Clock and Reset module generates the de-
vice reset by using reset input signals coming from an exter-
nal reset, the watchdog timer, or the SDI debugging
interface. A power-on reset (POR) circuit eliminates the
need for an external RC network. The POR circuit gener-
ates an internal reset of sufficient length if the power supply
rise time specification is met.
3.24 DMA CONTROLLER
The Direct Memory Access Controller (DMAC) can speed
up data transfer between memory and I/O devices or be-
tween two regions of memory, as compared to data trans-
fers performed directly by the CPU. Cycle stealing allows
the CPU and the DMAC to interleave access to the CPU
core bus for greater utilization of the available bandwidth.
The following on-chip modules can assert a DMA request to
the DMA controller:
• USART 0 (2 request channels)
• UART 1/2/3 (6 request channels)
• Advanced Audio Interface (6 request channels)
• CVSD/PCM Converter 0/1 (8 request channels)
• Microwire/SPI 0/1 (4 request channels)
• ACCESS.bus 0/1 (2 request channels)
• Codec (4 request channels)
• I2S Interface (4 request channels)
The DSP has its own DMA controller which can be config-
ured to accept DMA requests from peripherals on the
shared audio peripheral APB bus. The USB controller also
has its own DMA controller, which operates on the CPU
core bus.
3.25 SERIAL DEBUG INTERFACE
The Serial Debug Interface module (SDI module) provides
a JTAG-based serial link to an external debugger, for exam-
ple running on a PC. In addition, the SDI module integrates
an on-chip debug module, which allows the user to set up to
eight hardware breakpoints on instruction execution and
data transfer. The SDI module can act as a CPU bus master
to access all memory-mapped resources, such as RAM and
peripherals. Therefore it also allows for fast program code
download using the JTAG interface.
3.26 DEVELOPMENT SUPPORT
In addition to providing the features needed for the next gen-
eration of embedded Bluetooth products, the CP3SP33 de-
vices are backed up by the software resources that
designers need for rapid product development, including an
operating system, Bluetooth protocol stack implementation,
peripheral drivers, reference designs, and an integrated de-
velopment environment. Combined with National’s
LMX5251 Bluetooth radio transceiver, the CP3SP33 devic-
es provide a total Bluetooth system solution.
National Semiconductor offers a complete and industry-
proven application development environment for CP3SP33
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth Protocol Stack, and Applica-
tion Software. See your National Semiconductor sales rep-
resentative for current information on availability and
features of emulation equipment and evaluation boards.
www.DataSheet4U.com
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly used
in accordance with instructions for use provided in the labeling,
can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to af-
fect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship
Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no “Banned
Substances” as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
National Semiconductor
Corporation
Tel: 1-800-272-9959
Fax: 1-800-737-7018
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Deutsch Tel:
+49 (0) 69 9508 6208
English Tel:
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Tel: 65-254-4466
Fax: 65-250-4466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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共有リンク

Link :


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CP3SP33

CP3SP33 Processor w Cache DSPBluetooth USB Dual CAN Interface

Texas Instruments
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CP3SP33

Connectivity Processor

National Semiconductor
National Semiconductor


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