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PDF HD404638RF Data sheet ( Hoja de datos )
| Número de pieza | HD404638RF | |
| Descripción | 4-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD404638RF (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
www.DataSheet4U.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Pin Arrangement
HD404639R Series
RD0 /COMP0
RD1 /COMP1
RD2 /COMP2
RD3 /COMP3
RE0 /VCref
TEST
OSC1
OSC2
RESET
X1
X2
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
80 7978 7776 757473727170 69686766 65
1 64
2 63
3 62
4 61
5 60
6 59
7 58
8 57
9 56
10 55
11 54
12
13
FP-80B
53
52
14 51
15 50
16 49
17 48
18 47
19 46
20 45
21 44
22 43
23 42
24 41
25 2627 2829 303132333435 36373839 40
R9 1
R9 0
R8 3
R8 2
R8 1
R8 0
R7 3
R7 2
R7 1
R7 0
R6 3
R6 2
R6 1
R6 0
R5 3 /SO2
R5 2 /SI2
R5 1 /SCK2
R5 0
R4 3 /SO1
R4 2 /SI1
R4 1 /SCK1
R4 0 /EVND
R3 3 /EVNB
R3 2 /TOD
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(Top view)
3
5 Page 
HD404639R Series
Bit 3
IM0
0 (IM of INT0)
Bit 2
IF0
(IF of INT0)
Bit 1
RSP
(Reset SP bit)
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT1)
$000
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
IMS1
3 (IM of serial
interface 1)
IFS1
(IF of serial
interface 1)
IMTD
(IM of timer D)
IFTD
(IF of timer D)
$003
Interrupt control bits area
Bit 3
DTON
32 (Direct transfer
on flag)
RAME
33 (RAM enable
flag)
34
IM3
(IM of INT3)
IMS2
35 (IM of serial
interface 2)
Bit 2
Not used
Not used
Bit 1
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
IF3
(IF of INT3)
IFS2
(IF of serial
interface 2)
IM2
(IM of INT2)
IM4
(IM of INT4)
Register flag area
Bit 0
LSON
(Low speed
on flag)
ICSF
(Input capture
status flag)
IF2
(IF of INT2)
IF4
(IF of INT4)
$020
$021
$022
$023
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
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IE
IM
LSON
IF
ICSF
ICEF
RAME
RSP
WDON
DTON
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Allowed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD404638RF.PDF ] | |
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