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PDF UPD46128953-X Data sheet ( Hoja de datos )
| Número de pieza | UPD46128953-X | |
| Descripción | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION | |
| Fabricantes | NEC | |
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
μPD46128953-X
128M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 32-BIT
ADDRESS / DATA MULTIPLEXED
EXTENDED TEMPERATURE OPERATION
Description
The μPD46128953-X is a high speed, low power, 134,217,728 bits (4,194,304 words by 32 bits) CMOS Mobile
Specified RAM featuring synchronous burst read and synchronous burst write function.
The μPD46128953-X realizes high performance with the SDR interface, command and data inputs / outputs are
synchronized the rising edge of clock.
The μPD46128953-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
• 4,194,304 words by 32 bits organization
• Low voltage operation: 1.7 to 2.0 V (1.85±0.15 V)
• Operating ambient temperature: TA = −25 to +85 °C
• Synchronous burst mode
Burst length
: 8 double words (Wrap)
Burst sequence
: Linear burst
Maximum clock frequency : 83 / 66 MHz
• SDR (Single Data Rate) Architecture
One data transfers per one clock cycle
All inputs/outputs are synchronized with the positive edge of the clock
• Write data mask (DM) for write operation
• Output Enable: /OE pin
• Chip Enable input: /CE1 pin
• Standby Mode input: CE2 pin
• Standby Mode 1: Normal standby (Memory cell data hold valid)
www.Da•taSSthaenedt4bUy.cMoomde 2: Density of memory cell data hold is variable
μPD46128953
Clock
frequency
MHz
(MAX.)
-E12X Note
83
-E15X
66
Note Under consideration
Operating
supply
voltage
V
1.7 to 2.0
Operating
ambient
temperature
°C
−25 to +85
Supply current
At operating mA
At standby μA
(MAX.)
(MAX.)
60 T.B.D.
55
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M17506EJ1V1DS00 (1st edition)
Date Published September 2005 CP (K)
Printed in Japan
2005
1 page  
Symbol
DM0 to DM3
/WAIT
VDD
VSS
VDDQ
VSSQ
NC
μPD46128953-X
(2/2)
Description
Synchronous write data mask input.
These signals can mask write data during burst write.
To input data mask, the setup time and hold time must be satisfied at the rising edge of CLK.
Data mask can be controlled in byte units.
DM0: A/DQ0 to ADQ7
DM1: A/DQ8 to ADQ15
DM2: A/DQ16 to ADQ21, DQ22 to DQ23
DM3: DQ24 to DQ31
Synchronous wait output.
/WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write
This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready.
The wait signal is output at the rising edge of CLK.
Supply voltage:
Usually, the supply voltage is 1.85 V. Refer to DC Characteristics and Recommended Operation
Conditions.
Supply voltage:
Ground
Supply voltage:
Supply voltage for DQ. Usually, this voltage is 1.85 V. Refer to DC Characteristics and Recommended
Operation Conditions.
Supply voltage:
Ground for DQ.
No connection
Some signals can be applied because this pin is not internally connected.
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Preliminary Data Sheet M17506EJ1V1DS
5
5 Page 
μPD46128953-X
2. Partial Refresh
2. 1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 128M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2. 2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 64M bits, 32M bits, 16M bits, and 0M
bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the
mode register, these settings are retained until they are set again, while applying the power supply. However, the mode
register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 4. Mode Register Settings.)
2. 3 Standby Mode Status Transition
In Standby Mode 1, /CE1 and CE2 are HIGH. In Standby Mode 2, CE2 is LOW. In Standby Mode 2, if 0M bit is set as
the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal
operation from Standby Mode 2. When the density has been set to 64M bits, 32M bits, or 16M bits in Standby Mode 2, it
is not necessary to perform initialization to return to normal operation from Standby Mode 2.
For the timing charts, refer to Figure 9-1. Standby Mode 2 (data hold: 64M bits / 32M bits / 16M bits) Entry / Exit
Timing Chart, Figure 9-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
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Preliminary Data Sheet M17506EJ1V1DS
11
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