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AT52SC1284JのメーカーはATMEL Corporationです、この部品の機能は「(AT52SC1283J / AT52SC1284J) 128-Mbit Flash + 32-Mbit/64-Mbit」です。 |
部品番号 | AT52SC1284J |
| |
部品説明 | (AT52SC1283J / AT52SC1284J) 128-Mbit Flash + 32-Mbit/64-Mbit | ||
メーカ | ATMEL Corporation | ||
ロゴ | |||
このページの下部にプレビューとAT52SC1284Jダウンロード(pdfファイル)リンクがあります。 Total 30 pages
Module Features
• 128-Mbit Burst/Page Flash + 32-Mbit/64-Mbit PSRAM
• Single 88-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
• 1.7V to 1.95V VCC
• 1.8V to 1.95V for VCCQ and PVCC
128-Mbit Flash Features
• 8M x 16 Organization
• High Performance
– Random Access Time – 70 ns, 85 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
• Sector Erase Architecture
– Sixteen 4K Word Sectors with Individual Write Lockout
– Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout
• Typical Sector Erase Time: 32K Word Sectors – 800 ms; 4K Word Sectors – 200 ms
• Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one
Planes not Being Programmed/Erased
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 30 mA Active
– 20 µA Standby
• VPP Pin for Write Protection and Accelerated Program Operations
• RESET Input for Device Initialization
• Two Protection Registers (128 Bits + 2,048 Bits)
• Common Flash Interface (CFI)
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• 1.7V to 1.95V Operating Voltage
Asynchronous/Page PSRAM Features
• 32-Mbit (2M Word x 16)/64-Mbit (4M Word x 16)
• 70 ns Random Access Time
• 30 ns Page Read Cycle Time
• 1.8V to 1.95V Operating Voltage
• <10 µA Deep Standby Power
128-Mbit Flash
+ 32-Mbit/64-Mbit
PSRAM
Stack Memory
AT52SC1283J
AT52SC1284J
Preliminary
Stack Module Memory Contents
Device
AT52SC1283J
AT52SC1284J
Memory Combination
128M Flash + 32M PSRAM
128M Flash + 64M PSRAM
3530B–STKD–2/4/05
1 Page 3. Pin Configurations
AT52SC1283J/1284J [Preliminary]
3.1 88-ball CBGA Top View
Pin Name
A0 - A22
I/O0 - I/O15
CE
OE
WE
AVD
CLK
RST
WP
VPP
WAIT
VCC
PCS1
ZZ
VCCQ
PLB
PUB
POE
PWE
PVCC
NC
VSS
Function
Addresses
Data Inputs/Outputs
Flash Chip Enable
Flash Output Enable
Flash Write Enable
Flash Address Latch Enable
Flash Clock
Flash Reset
Flash Write Protect
Flash Write Protection and Power Supply for
Accelerated Program Operation
Flash WAIT
Flash Power Supply
PSRAM Chip Select
PSRAM Deep Power-down
Output Power Supply
PSRAM Lower Byte Control
PSRAM Upper Byte Control
PSRAM Output Enable
PSRAM Write Enable
PSRAM Power Supply
No Connect
Device Ground (Common)
www.DataSheet4U.com
4. Absolute Maximum Ratings
Temperature under Bias ...................................-25°C to +85°C
Storage Temperature ......................................-55°C to +150°C
All Input Voltages except VPP (including NC Pins)
with Respect to Ground ............................. -0.2V to VCC + 0.3V
Voltage on VPP
with Respect to Ground ..................................-0.2V to + 10.0V
All Output Voltages
with Respect to Ground ............................. -0.2V to VCC + 0.3V
5. DC and AC Operating Range
Operating Temperature (Case)
VCC Power Supply
VCCQ, PVCC
12345678
A
NC NC
NC NC
B
A4 A18 A19 VSS VCC NC A21 A11
C
A5 PLB NC VSS NC CLK A22 A12
D
A3 A17 NC VPP PWE PCS1 A9 A13
E
A2 A7 NC WP AVD A20 A10 A15
F
A1 A6 PUB RST WE A8 A14 A16
G
A0 I/O8 I/O2 I/O10 I/O5 I/O13 WAIT NC
H
POE I/O0 I/O1 I/O3 I/O12 I/O14 I/O7 NC
J
NC OE1 I/O9 I/O11 I/O4 I/O6 I/O15 VCCQ
K
CE1 NC NC NC PVCC NC VCCQ ZZ
L
VSS VSS VCCQ VCC VSS VSS VSS VSS
M
NC NC
NC NC
Flash Only
PSRAM Only
Common
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
-25°C to 85°C
1.7V to 1.95V
1.8V to 1.95V
3530B–STKD–2/4/05
3
3Pages takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate
that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and
B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is
driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated
when the CE or OE signal is high.
In the “Burst Read Waveform” as shown on page 33, the valid address is latched at point A. For
the specified clock latency of three, data D13 is valid within 13 ns of clock edge B. The low-to-
high transition of the clock at point C results in D14 being read. The transition of the clock at
point D results in a burst read of D15. The clock transition at point E does not cause new data to
appear on the output lines because the WAIT signal goes low (B10 and B8 = 0) after the clock
transition, which signifies that the first boundary in the memory has been crossed and that new
data is not available. After a clock latency of three, the clock transition at point F does cause a
burst read of data D16 because the WAIT signal goes high (B10 and B8 = 0) after the clock tran-
sition indicating that new data is available. Additional clock transitions, like at point G, will
continue to result in burst reads.
6.7 Fixed-Length Burst Reads
During a fixed-length burst mode read, four, eight or sixteen words of data may be burst from the
device, depending upon the configuration. The device supports a linear burst mode. The burst
sequence is shown on page 22. When operating in the linear burst read mode (B7 = 1) with the
burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence
crosses the first 16-word boundary in the memory. If the starting is D0 - D12, there is no delay. If
the starting address is D13 - D15, an output delay equal to the initial clock latency is incurred.
The delay takes place only once, and only if the burst sequence crosses a 16-word boundary.
To indicate that the device is not ready to continue the burst, the device will drive the WAIT pin
low (B10 and B8 = 0) during the clock cycles in which new data is not being presented. Once the
WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be
tri-stated when the CE or OE signal is high.
www.DataSheet4U.com
The “Four-word Burst Read Waveform” on page 34 illustrates a fixed-length burst cycle. The
valid address is latched at point A. For the specified clock latency of four, data D0 is valid within
13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read.
Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the
read cycle. There is no output delay in the burst access wrap mode (B3 = 0).
6.8 Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst oper-
ation if the system needs to use the Flash address and data bus for other purposes. Burst
accesses can be suspended during the initial latency (before data is received) or after the device
has output data. When a burst access is suspended, internal array sensing continues and any
previously latched internal data is retained.
Burst Suspend occurs when CE is asserted, the current address has been latched (either rising
edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be halted
when it is at VIH or VIL. To resume the burst access, OE is reasserted and the CLK is restarted.
Subsequent CLK edges resume the burst sequence where it left off.
Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT signal
reverts to a high-impedance state when OE is deasserted. See “Burst Suspend Waveform” on
page 34.
6 AT52SC1283J/1284J [Preliminary]
3530B–STKD–2/4/05
6 Page | |||
ページ | 合計 : 30 ページ | ||
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部品番号 | 部品説明 | メーカ |
AT52SC1284J | (AT52SC1283J / AT52SC1284J) 128-Mbit Flash + 32-Mbit/64-Mbit | ATMEL Corporation |