DataSheet.jp

WV3HG264M72EER-PD4 の電気的特性と機能

WV3HG264M72EER-PD4のメーカーはWhite Electronic Designsです、この部品の機能は「1GB - 2x64Mx72 DDR2 SDRAM REGISTERED」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3HG264M72EER-PD4
部品説明 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




このページの下部にプレビューとWV3HG264M72EER-PD4ダウンロード(pdfファイル)リンクがあります。
Total 11 pages

No Preview Available !

WV3HG264M72EER-PD4 Datasheet, WV3HG264M72EER-PD4 PDF,ピン配置, 機能
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM REGISTERED, SO-DIMM, w/PLL
FEATURES
Registered 200-pin (SO-DIMM), Small-Outline dual
in-line memory module
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Differential clock inputs (CK, CK#)
Programmable CAS# latency (CL): 3, 4, 5*, and 6*
Posted CAS# additive latency: 0, 1, 2, 3 and 4
On-die termination (ODT)
7.8µs average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Utilizes 512Mb DDR2 SDRAM components
Auto & self refresh (64ms: 8,192 cycle refresh)
wwwG.DoaltdaSehdegeet4cUo.ncotamcts
Dual Rank
RoHS compliant
JEDEC proposed Pin-out
Package
• 200 Pin SO-DIMM: 30.00mm (1.181") TYP.
DESCRIPTION
The WV3HG264M72EER is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit DDR2 Synchronous
DRAMs in FBGA packages, mounted on a 200-pin SO-
DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
April 2006
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3HG264M72EER-PD4 pdf, ピン配列
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
RCS1#Җ
RCS0#
DQS0
DQS0#
DM0
DQS1
DQS1#
DM1
DQS2
DQS2#
DM2
DQS3
DQS3#
DM3
DQS8
www.DataSheet4U.coDmQS8#
DM8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS4#
DM4
CS#Җ DQS DQS#Җ
DQS5
DQS5#
DM5
CS#Җ DQS DQS#Җ
DQS6
DQS6#
DM6
CS#Җ DQS DQS#Җ
DQS7
DQS7#
DM7
CS#Җ DQS DQS#Җ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
CS0#
CS1#
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RESET#
PCK**
PCK#**
1:2
R
E
G
I
S
T
E
R
RST#
RCS0# CS# : DDR2 SDRAMs
RCS1# CS# : DDR2 SDRAMs
RBA0 - RBA1 BA0-BA1 : DDR2 SDRAMs
RA0 - RA13 A0-A13 : DDR2 SDRAMs
RRAS# RAS# : DDR2 SDRAMs
RCAS# CAS# : DDR2 SDRAMs
RWE# WE# : DDR2 SDRAMs
RCKE0 CKE : DDR2 SDRAMs
RCKE1 CKE : DDR2 SDRAMs
RODT0 ODT : DDR2 SDRAMs
RODT1 ODT : DDR2 SDRAMs
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#Җ DQS DQS#Җ
Serial PD
SCL
WP A0 A1 A2
SDA
SA0 SA1 SA2
VCCSPD
VCC/VCCQ
VREF
VSS
120
CK
CK#
RESET#Ҙ **
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
CK
PLL
CK#
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
REGISTER X 2
** RESET#, PCK and PCK# connect to both Registers. Other signals connect to one of two Registers.
Note: All resistor values are 22 ohms ±5% unless otherwise specified.
April 2006
Rev. 2
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3HG264M72EER-PD4 電子部品, 半導体
White Electronic Designs WV3HG264M72EER-PD4
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
VCC = +1.8V ± 0.1V
Symbol Proposed Conditions
806
ICC0* Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
ICC1*
ICC2P*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD
TBD
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD
ICC2N**
ICC3P**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING Slow PDN Exit MRS(12) = 1
TBD
TBD
TBD
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
www.DatatRSAhSmeaext(4ICUC.)c, toRmP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
TBD
TBD
TBD
ICC6** Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
TBD
ICC7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
TBD
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
665 534 403 Units
1,337 1,292 1,292 mA
1,472 1,427 1,427 mA
644 644 644 mA
1,130 1,040 1,040 mA
1,220 1,130 1,130 mA
1,040 1,040 1,040
716 716 716
mA
mA
1,490 1,400 1,400 mA
1,832 1,652 1,562 mA
1,877 1,697 1,562 mA
3,200 3,020 3,020 mA
144 144 144 mA
2,552 2,552 2,552 mA
April 2006
Rev. 2
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



ページ 合計 : 11 ページ
 
PDF
ダウンロード
[ WV3HG264M72EER-PD4 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
WV3HG264M72EER-PD4

1GB - 2x64Mx72 DDR2 SDRAM REGISTERED

White Electronic Designs
White Electronic Designs


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap