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WV3HG264M64EEU-D6 の電気的特性と機能

WV3HG264M64EEU-D6のメーカーはWhite Electronic Designsです、この部品の機能は「1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3HG264M64EEU-D6
部品説明 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3HG264M64EEU-D6 Datasheet, WV3HG264M64EEU-D6 PDF,ピン配置, 機能
White Electronic Designs WV3HG264M64EEU-D6
ADVANCED*
1GB – 2x64Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 MT/s DDR2
SDRAM components
VCC = VCCQ = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual Rank
RoHS compliant
Package option
• 240 Pin DIMM
• PCB – 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG264M64EEU is a 2x64Mx64 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of sixteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
December 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3HG264M64EEU-D6 pdf, ピン配列
White Electronic Designs WV3HG264M64EEU-D6
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQ24
DM/
RDQS
I/O 0
DQ25
I/O 1
DQ26
I/O 2
DQ27
I/O 3
DQ28
I/O 4
DQ29
I/O 5
www.DataSheDDeQQ33t014U.coIIm//OO 67
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DQS5
DQS5#
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS7#
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
VCCSPD
VCC/VCCQ
VREF
VSS
CS0#
CS1#
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
S0# : DDR2 SDRAMs
S1# : DDR2 SDRAMs
BA0 - RBA1 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
ODT : DDR2 SDRAMs
SCL Serial PD
WP WPA0 A0 A1A1 AA22
SA0 SA1 SA2
SDA
*Clock Wiring
Clock
Input
*CK0/CK0#
*CK1/CK1#
*CK2/CK2#
DDR2 SDRAMs
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ, DM, DQS, DQS# resistors: 5.1 Ohms +/- 5%
2. BAx, Ax, RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5%
NOTE: All resistor values are 22 ohms unless otherwise specified.
December 2005
Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3HG264M64EEU-D6 電子部品, 半導体
White Electronic Designs WV3HG264M64EEU-D6
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Symbol Proposed Conditions
806 665 534 403 Units
Operating one bank active-precharge current;
ICC0* tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 744 704 704 mA
Operating one bank active-read-precharge current;
ICC1*
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS MIN(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
TBD 864 824 824 mA
Precharge power-down current;
ICC2P** All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; TBD 128 128 128 mA
Data bus inputs are FLOATING
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
TBD 560 480 480 mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 640 560 560 mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
TBD 480 480 480 mA
TBD 192 192 192 mA
Active standby current;
ICC3N**
All banks open; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
TBD
880
800
800
mA
inputs are SWITCHING
Operating burst write current;
ICC4W**
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
www.DatabSushieneput4tsUa.rceoSmWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
ICC4R*
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK
= tCK(ICC), tRAS = tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
TBD 1184 1024 944
mA
TBD 1224 1064 944
mA
Burst auto refresh current;
ICC5B**
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
TBD
2400 2240 2240
mA
inputs are SWITCHING
Self refresh current;
ICC6*
CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
Normal
FLOATING
TBD 128 128 128 mA
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
ICC7* tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
switching.
TBD
1824 1824 1824
mA
* Value calculated as one module rank in thes operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition
NOTES:
• ICC specifications were calculated using SAMSUNG components. Other manufactures DRAMs may have different values.
December 2005
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3HG264M64EEU-D4

1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs
WV3HG264M64EEU-D6

1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs


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