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WV3HG2128M72EEU-AD4 の電気的特性と機能

WV3HG2128M72EEU-AD4のメーカーはWhite Electronic Designsです、この部品の機能は「2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3HG2128M72EEU-AD4
部品説明 2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3HG2128M72EEU-AD4 Datasheet, WV3HG2128M72EEU-AD4 PDF,ピン配置, 機能
White Electronic Designs WV3HG2128M72EEU-AD4
ADVANCED*
2GB – 2x128Mx72 DDR2 SDRAM UNBUFFERED, ECC w/PLL
FEATURES
200-pin, dual in-line memory module (SO-DIMM)
Support ECC error detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
VCC = VCCQ = 1.8V ±0.1V
1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Differential clock inputs (CK, CK#)
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Dual Rank
RoHS compliant
Package option
www.Da2t0a0ShPeinet4SUO.c-oDmIMM
• PCB – 30.00mm (1.181") Max
DESCRIPTION
The WV3HG2128M72EEU is a 2x128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 128Mx8 bit stacked BGA with
8 banks DDR2 Synchronous DRAMs in FBGA packages,
mounted on a 200-pin SO-DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
PC2-6400*
400MHz
6-6-6
PC2-5300*
333MHz
5-5-5
PC2-4200
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
February 2006
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3HG2128M72EEU-AD4 pdf, ピン配列
White Electronic Designs WV3HG2128M72EEU-AD4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
www.DataSheet4U.coDDmQQ2390
DQ31
DQS8
DQS8#
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0#
CS1#
BA0 - BA2
A0 - A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5#
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS7#
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
I/O 4 I/O 4
I/O 5 I/O 5
I/O 6 I/O 6
I/O 7 I/O 7
DM
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
I/O 4 I/O 4
I/O 5 I/O 5
I/O 6 I/O 6
I/O 7 I/O 7
DM
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
I/O 4 I/O 4
I/O 5 I/O 5
I/O 6 I/O 6
I/O 7 I/O 7
DM
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0 I/O 0
I/O 1 I/O 1
I/O 2 I/O 2
I/O 3 I/O 3
I/O 4 I/O 4
I/O 5 I/O 5
I/O 6 I/O 6
I/O 7 I/O 7
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0# : DDR2 SDRAMs
CS1# : DDR2 SDRAMs
BA0 - BA2 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE0 : DDR2 SDRAMs
CKE1 : DDR2 SDRAMs
ODT0 : DDR2 SDRAMs
ODT1 : DDR2 SDRAMs
CK0
CK0#
Serial PD
SCL
WP A0 A1 A2
SDA
SA0 SA1
SA2
VCCSPD
VCC
VREF
VSS
120Ω
PLL CK
CK#
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
NOTE: All resistor values are 22 ohms unless otherwise specified.
February 2006
Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3HG2128M72EEU-AD4 電子部品, 半導体
White Electronic Designs WV3HG2128M72EEU-AD4
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
0°C ≤ TCASE < +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Symbol Proposed Conditions
806
ICC0*
ICC1*
ICC2P**
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
TBD
TBD
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
TBD
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
TBD
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
TBD
TBD
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
www.DataShinepeutts4Uar.ecSoWmITCHING; Data bus inputs are SWITCHING
TBD
ICC4R*
ICC5**
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC),
tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
TBD
ICC6** Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
TBD
ICC7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid TBD
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R;
Refer to the following page for detailed timing conditions
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in the operating condition.
665 534 403 Units
1,218 1,173 1,128 mA
1,308 1,263 1,218 mA
516 516 516 mA
1,020 930 930 mA
1,110 1,020 1,020 mA
840 750 750 mA
516 516 516 mA
1,200 1,110 1,110 mA
1,803 1,578 1,443 mA
1,803 1,578 1,443 mA
4,260 4,170 4,080 mA
108 108 108 mA
3,108 2,928 2,748 mA
February 2006
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3HG2128M72EEU-AD4

2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs


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