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WV3EG64M64ETSU-D4 の電気的特性と機能

WV3EG64M64ETSU-D4のメーカーはWhite Electronic Designsです、この部品の機能は「512MB - 64Mx64 DDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3EG64M64ETSU-D4
部品説明 512MB - 64Mx64 DDR SDRAM
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3EG64M64ETSU-D4 Datasheet, WV3EG64M64ETSU-D4 PDF,ピン配置, 機能
White Electronic Designs WV3EG64M64ETSU-D4
PRELIMINARY*
512MB – 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM
FEATURES
Fast data transfer rate: PC3200 & PC2700
Clock speeds of 200MHz & 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency : DDR400 (3 clock),
DDR333 (2.5 clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh, 7.8µs refresh interval (8K
(64ms refresh)
Serial presence detect (SPD) with EEPROM
Serial presence detect with EEPROM
VCC = VCCQ = +2.5V ±0.2V (166MHz)
VCC = VCCQ = +2.6V ±0.1V (200MHz)
Gold edge contacts
JEDEC standard 200 pin, small-outline, SO-DIMM
package
• PCB height option:
D4: 31.75 mm (1.25”) TYP
www.DataSheet4U.com
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3EG64M64ETSU is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs TSOP-II packages mounted on a 200 pin FR4
substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR400@CL=3
200MHz
3-3-3
DDR333@CL2.5
166MHz
2.5-3-3
March 2006
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3EG64M64ETSU-D4 pdf, ピン配列
White Electronic Designs WV3EG64M64ETSU-D4
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
www.DataSheet4U.comDDQQ2289
DQ30
DQ31
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS4
DM4
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQS5
DM5
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQS6
DM6
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQS7
DM7
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
CKE0
BA0 - BA1
A0 - A12
RAS#
CAS#
WE#
CKE0: DDR SDRAMs
BA0 - BA1: DDR SDRAMs
A0 - A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
WE#: DDR SDRAMs
VCCSPD
VCC/VCCQ
VREF
VSS
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
Note: 1. All resistor values are 22Ω unless otherwise specified.
March 2006
Rev. 0
3
SCL
SP
Serial PD
A0 A1 A2
SA0 SA1 SA2
SDA
CK0
CK0#
CK1
CK1#
120 Ohms
120 Ohms
DDR SDRAM x 4
DDR SDRAM x 4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3EG64M64ETSU-D4 電子部品, 半導体
White Electronic Designs WV3EG64M64ETSU-D4
PRELIMINARY
ICC SPECIFICATIONS AND CONDITIONS
0°C ≤ TA ≤ +70°C DDR400: VCC = VCCQ = +2.6V ±0.1V
Symbol Parameter/Condition
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN);
ICC0 DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
ICC1
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN);
tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
ICC2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE =
ICC2F HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS,
and DM
ICC3P
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS
ICC3N (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
ICC4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address
ICC4W
and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
ICC5 AUTO REFRESH BURST CURRENT:
tREFC = tRFC (MIN)
ICC6 SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge,
ICC7 tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
Nwowtesw: .DataSheet4U.com
ICC parameters are based on SAMSUNG components. Other DRAM manufactures parameter may be different
Max
DDR400
@CL=3
960
1,200
40
240
360
480
1,240
1,400
1,760
40
3,080
Max
DDR333
@CL=2.5
840
Units
mA
1,080
40
mA
mA
240 mA
200 mA
360 mA
1,120
mA
1,200
1,640
40
2,880
mA
mA
mA
mA
March 2006
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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共有リンク

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部品番号部品説明メーカ
WV3EG64M64ETSU-D3

512MB - 64Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs
WV3EG64M64ETSU-D4

512MB - 64Mx64 DDR SDRAM

White Electronic Designs
White Electronic Designs


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