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WV3EG64M64ETSU-D3 の電気的特性と機能

WV3EG64M64ETSU-D3のメーカーはWhite Electronic Designsです、この部品の機能は「512MB - 64Mx64 DDR SDRAM UNBUFFERED」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3EG64M64ETSU-D3
部品説明 512MB - 64Mx64 DDR SDRAM UNBUFFERED
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3EG64M64ETSU-D3 Datasheet, WV3EG64M64ETSU-D3 PDF,ピン配置, 機能
White Electronic Designs
WV3EG64M64ETSU-D3
PRELIMINARY*
512MB – 64Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
• VCC = VCCQ = +2.5V ±0.2V
184 pin DIMM package
• D3 PCB height: 28.58mm (1.125")
DESCRIPTION
The WV3EG64M64ETSU is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
August 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3EG64M64ETSU-D3 pdf, ピン配列
White Electronic Designs
WV3EG64M64ETSU-D3
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
www.DataSheet4U.com
CS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM CS# DQS
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM CS# DQS
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM CS# DQS
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
DM
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
CS#
DQS
SCL
WP
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
Clock Wiring
Clock
Input
DDR SDRAMs
CK0, CK0#
CK1, CK1#
CK2, CK2#
2 DDR SDRAMs
3 DDR SDRAMs
3 DDR SDRAMs
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
WE#
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
VCCSPD
VCC/VCCQ
VREF
VSS
*Clock Net Wiring
R = 120 Ohm
Card
Edge
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DRAM 1
1.5PF
DRAM 3
1.5PF
DRAM 5
1.5PF
NOTE: All datalines are terminated through a 22 ohm series resistor.
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown.
August 2005
Rev. 1
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3EG64M64ETSU-D3 電子部品, 半導体
White Electronic Designs
WV3EG64M64ETSU-D3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data into Read command
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
CL = 2.5
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
wAwddwre.DssaatnadSChoenetrto4lUIn.pcuotmsetup time (fast)
Address and Control Input hold time (fast)
Address and Control Input setup time (slow)
Address and Control Input hold time (slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Output Slew Rate Matching Ratio (rise to fall)
Note: These specifications apply to modules built with Samsung components only.
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tISF
tIHF
tHZS
tLZS
tSLMR
335
Min Max
60
72
42 70K
18
18
12
15
1
6 12
0.45 0.55
0.45 0.55
-0.6 +0.6
-0.7 +0.7
— 0.45
0.9 1.1
0.4 0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
-0.7 +0.7
-0.7 +0.7
0.67 1.5
Unit
ns
ns
ns
ns
ns
ns
ns
tCK
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
August 2005
Rev. 1
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3EG64M64ETSU-D3

512MB - 64Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs
WV3EG64M64ETSU-D4

512MB - 64Mx64 DDR SDRAM

White Electronic Designs
White Electronic Designs


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