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WV3EG128M72EFSR-D3 の電気的特性と機能

WV3EG128M72EFSR-D3のメーカーはWhite Electronic Designsです、この部品の機能は「1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL」です。


製品の詳細 ( Datasheet PDF )

部品番号 WV3EG128M72EFSR-D3
部品説明 1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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WV3EG128M72EFSR-D3 Datasheet, WV3EG128M72EFSR-D3 PDF,ピン配置, 機能
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED*
1GB – 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA
FEATURES
Double-data-rate architecture
DDR266 and DDR333
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and
166MHz)
184 pin DIMM package
PCB height:
• D3: 29.97mm (1.18")
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
www.DatIandSuhsteriaeltt4emUp.ecroatmure options
DESCRIPTION
The WV3EG128M72EFSR is a 128Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of eighteen
64Mx8 DDR components in FBGA packages mounted on
a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
March 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 Page





WV3EG128M72EFSR-D3 pdf, ピン配列
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
DQS0
DM0/DQS9
RCS0#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
RCS1#
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DQS5
DM5/DQS14
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQ24
DQ25
DQ26
DM
I/O7
I/O6
I/O1
DQ27
I/O0
DQ28
I/O5
DQ29
DQ30
I/O4
I/O3
www.DataSheeDt4QU31.com I/O2
DQS4
DM4/DQS13
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
CS# DQS
CS# DQS
CS# DQS
CS# DQS
CS0#
CS1#
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
CKE1
WE#
R RCS0#
E RCS1#
G
I
RBA0-RBA1
S RA0-RA12
T RRAS#
E
R
RCAS#
RCKE0
RCKE1
RWE#
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DQS6
DM6/DQS15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS7
DM6/DQS16
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS8
DM7/DQS17
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
CS# DQS
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
CS# DQS
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
CS# DQS
BA0-BA1: SDRAMs
A0-A12: SDRAMs
RAS#: SDRAMs
CAS#: SDRAMs
CKE: SDRAMs
CKE: SDRAMs
WE#: DQRAMs
CK0
CK0#
120
PLL
SCL
WP
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2
V CCSPD
VCCQ
SPD
DDR SDRAMS
PCK
PCK#
RESET#
VCC
VREF
DDR SDRAMS
DDR SDRAMS
Note: All resistor values are 22Ω unless otherwise indicated.
VSS DDR SDRAMS
March 2005
Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


3Pages


WV3EG128M72EFSR-D3 電子部品, 半導体
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and register power
Parameter
Operating Current
Symbol
IDD0
Operating Current
IDD1
Precharge Power-
Down Standby Current
Idle Standby Current
IDD2P
IDD2F
Active Power-Down
Standby Current
Active Standby Current
IDD3P
IDD3N
Operating Current
Operating Current
IDD4R
IDD4W
Auto Refresh Current
IDD5
Self Refresh Current
IDD6
www.DataSheet4U.com
Operating Current
IDD7A
Conditions
One device bank; Active - Precharge; tRC=tRC (MIN);
tCK=tCK (MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
once every two cycles.
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and
control inputs changing once per clock cycle.
All device banks idle; Power-down mode; tCK=tCK (MIN);
CKE=(low)
CS# = High; All device banks idle; tCK=tCK (MIN); CKE
= high; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM.
One device bank active; Power-Down mode; tCK (MIN);
CKE=(low)
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
tRC = tRC (MIN)
CKE 0.2V
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
DDR333@
CL=2.5
Max
4725
5265
180
1930
1260
2110
5355
5535
7640
455
9675
DDR266@
CL=2
Max
4725
5265
180
1930
1260
2110
5355
5175
7605
455
9585
DDR266@
CL=2.5
Max
4725
Units
mA
5265 mA
180 rnA
1930 mA
1260 mA
2110 mA
5355 mA
5175 rnA
7605 mA
455 mA
9585 mA
March 2005
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page



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部品番号部品説明メーカ
WV3EG128M72EFSR-D3

1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL

White Electronic Designs
White Electronic Designs


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