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PDF MT42C4256 Data sheet ( Hoja de datos )
| Número de pieza | MT42C4256 | |
| Descripción | 256K X 4 VRAM 256K x 4 DRAM | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
256K X 4 VRAM
256K x 4 DRAM
with 512K x 4 SAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-89497
• MIL-STD-883
FEATURES
• Class B High-Reliability Processing
• DRAM: 262144 Words × 4 Bits
SAM: 512 Words × 4 Bits
• Single 5-V Power Supply (±10% Tolerance)
• Dual Port Accessibility–Simultaneous and Asynchronous Access
From the DRAM and SAM Ports
• Bidirectional-Data-Transfer Function Between the DRAM and the
Serial-Data Register
• 4 × 4 Block-Write Feature for Fast Area Fill Operations; As Many
as Four Memory Address Locations Written per Cycle From an
On-Chip Color Register
• Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Write-Per-Bit Modes to Simplify System Design
• Enhanced Page-Mode Operation for Faster Access
• CAS-Before-RAS (CBR) and Hidden Refresh Modes
• All Inputs/Outputs and Clocks Are TTL Compatible
• Long Refresh Period: Every 8 ms (Max)
• Up to 33-MHz Uninterrupted Serial-Data Streams
• 3-State Serial I/Os Allow Easy Multiplexing of Video-Data
Streams
• 512 Selectable Serial-Register Starting
• Split Serial-Data Register for Simplified Real-Time Register Reload
OPTIONS
MARKING
• Timing
100ns, 30ns/27ns
-10
120ns, 35ns/35ns
-12
• Package(s)
Ceramic SOJ
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flat Pack
Ceramic ZIP
Ceramic LCC
MT Prefix
DCJ
C
EC
F
CZ
---
SMJ Prefix
---
JDM
HMM
---
SVM
HJM
For more products and information
please visit our web site at
www.DataSheet4wUw.cowm.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
28-Pin SOJ (DCJ)
28-Pin LCC (EC)
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
RAS\
A8
A6
A5
A4
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vss
27 SDQ4
26 SDQ3
25 SE\
24 DQ4
23 DQ3
22 DSF
21 CAS\
20 QSF
19 A0
18 A1
17 A2
16 A3
15 A7
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
RAS\
A8
A6
A5
A4
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vss
27 SDQ4
26 SDQ3
25 SE\
24 DQ4
23 DQ3
22 DSF
21 CAS\
20 QSF
19 A0
18 A1
17 A2
16 A3
15 A7
28-Pin ZIP (CZ)
DSF
DQ3
SDQ2
Vss
SDQ0
TRG\
DQ1
GND
A8
A5
Vcc
A3
A1
QSF
1
32
54
76
98
11 10
13 12
15 14
17 16
19 18
21
23
25
27
20
22
24
26
28
DQ2
SE\
SDQ3
SC
SDQ1
DQ0
W\
RAS\
A8
A4
A7
A2
A0
CAS\
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
RAS\
A8
A6
A5
A4
Vcc
28-Pin FP (F)
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
Vss
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
PIN NAME
(SMJ)
PIN NAME
(MT)
DESCRIPTION
A0 - A8
A0 - A8 Address Inputs
CAS\
CAS\ Column Enable
DQ0 - DQ3 DQ1 - DQ4 DRAM Data In-Out/Write-Mask Bit
SE\ SE\ Serial Enable
RAS\
RAS\ Row Enable
SC SC Serial Data Clock
SDQ0 - SDQ3 SDQ1 - SDQ4 Serial Data In-Out
TRG\
TR\ /OE\ Transfer Register/Q Output Enable
W\ ME\ /WE\ Write-Mask Select/Write Enable
DSF
DSF
Special Function Select
QSF
QSF
Split-Register Activity Status
Vcc Vcc 5V Supply
Vss Vss Ground
Ground (Important: Not Connected to
GND
NC internal Vss, Pin should be left open or
tied to ground.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
DETAILED SIGNAL DESCRIPTION VS. OPERATIONAL MODE
PIN
A0 - A8
CAS\
DQi
DSF
RAS\
SE\
SC
SDQ
TRG\
W\
QSF
NC/GND
Vcc
Vss
DRAM
Row, column address
Column enable, output enable
DRAM data I/O, write mask bits
Block-write enable
Persistent write-per-bit enable
Color-register load enable
Row enable
TRANSFER
Row, tap address
Tap-address strobe
Split-register enable
Alternative write-transfer enable
Row enable
Serial-in mode enable
Q output enable
Write enable, write-per-bit select
Transfer enable
Transfer-write enable
Make no external connection or tie
to system Vss
5V supply (typical)
Device ground
SAM
Serial enable
Serial clock
Serial-data I/O
Split register
Active status
OPERATION
Depending on the type of operation chosen, the signals of
the SMJ44C251B/MT42C4256 perform different functions. The
“Detailed Signal Description vs. Operational Mode” table
summarizes the signal descriptions and the operational modes
they control.
The SMJ44C251B/MT42C4256 has three kinds of
operations: random-access operations typical of a DRAM,
transfer operations from memory arrays to the SAM, and serial-
access operations through the SAM port. The signals used to
control these operations are described here, followed by
discussions of the operations themselves.
ROW-ADDRESS STROBE (RAS\)
RAS\ is similar to a chip enable because all DRAM cycles
and transfer cycles are initiated by the falling edge of RAS\.
RAS\ is a control input that latches the states of row address,
W\, TRG\, SE\, CAS\, and DSF onto the chip to invoke DRAM
and transfer functions.
COLUMN-ADDRESS STROBE (CAS\)
CAS\ is a control input that latches the states of column
address and DSF to control DRAM and transfer functions.
When CAS\ is brought low during a transfer cycle, it latches
the new tap point for the serial-data input or output. CAS\ also
acts as an output enable for the DRAM outputs DQ0–DQ3.
ADDRESS (A0–A8)
For DRAM operation, 18 address bits are required to
decode one of the 262144 storage cell locations. Nine row-
address bits are set up on A0–A8 and latched onto the chip on
the falling edge of RAS\. Nine column-address bits are set up
on A0–A8 and latched onto the chip on the falling edge of
CAS\. All addresses must be stable on or before the falling
OUTPUT ENABLE/TRANSFER SELECT (TRG\)
TRG\ selects either DRAM or transfer operation as RAS\
falls. For DRAM operation, TRG\ must be held high as RAS\
falls. During DRAM operation, TRG\ functions as an output
enable for the DRAM outputs DQ0–DQ3. For transfer
operation, TRG\ must be brought low before RAS\ falls.
edges of RAS\ and CAS\.
During the transfer operation, the states of A0–A8 are
latched on the falling edge of RAS\ to select one of the 512
rows where the transfer occurs. To select one of 512 tap points
(starting positions) for the serial-data input or output, the
www.DaatpapSrhoeperti4aUte.c9o-mbit column address (A0–A8) must be valid when
CAS\ falls.
WRITE-MASK SELECT, WRITE ENABLE (W\)
In DRAM operation, W\ enables data to be written to the
DRAM. W\ is also used to select the DRAM write-per-bit mode.
Holding W\ low on the falling edge of RAS\ invokes the write-
per-bit operation. The SMJ44C251B/MT42C4256 supports both
the normal write-per-bit mode and the persistent write-per-bit
mode.
CONTINUED
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
VRAM
SMJ44C251B
MT42C4256
TRANSFER OPERATION
Transfer operations between the memory arrays (DRAM)
and the data registers (SAM) are invoked by bringing TRG\ low
before RAS\ falls. The states of W\, SE\, and DSF, which are
also latched on the falling edge of RAS\, determine which transfer
operation is invoked. Figure 5 shows an overview of data flow
between the random and the serial interfaces.
As shown in the “Transfer-Operation Functions” table,
the SMJ44C251B/MT42C4256 supports five basic modes of
transfer operation:
• Register-to-memory transfer (normal write transfer,
SAM to DRAM)
• Alternate-write transfer (independent of the state of
SE\)
• Memory-to-register transfer (pseudo-transfer write).
Switches serial port from serial-out mode to serial-in
mode. No actual data transfer takes place between the
DRAM and the SAM.
• Memory-to-register transfer (normal-read transfer,
transfer entire contents of DRAM row to SAM)
• Split-register-read transfer (divides the SAM into a low
and a high half. Only one half is transferred to the
SAM while the other half is read from the serial I/O port.)
FIGURE 5: BLOCK DIAGRAM SHOWING ONE RANDOM AND ONE
SERIAL-I/O INTERFACE
www.DataSheet4U.com
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT42C4256.PDF ] | |
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