PDF IS61VF51232 Data sheet ( Hoja de datos )

Número de pieza	IS61VF51232
Descripción	512K x 32 Synchronous Flow-through Static RAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! ISSIIS61VF51232 IS61VF51236 IS61VF10018 ® 512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION October 2001 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Linear burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +2.5V, ±5% operation • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package DESCRIPTION The ISSI IS61VF51232, IS61VF51236, and IS61VF10018 are high-speed, low-power synchronous static RAMs de- signed to provide burstable, high-performance memory for communication and networking applications. The IS61VF51232 is organized as 524,288 words by 32 bits and the IS61VF51236 is organized as 524,288 words by 36 bits. The IS61VF10018 is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge- triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC www.DataSheet4U.com Parameter Clock Access Time Cycle Time Frequency -7.5 -8.5 7.5 8.5 8 10 125 100 Units ns ns MHz This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 ADVANCE INFORMATION Rev. 00A 10/23/01 1 1 page IS61VF51232 IS61VF51236 IS61VF10018 ISSI® PIN CONFIGURATION 119-pin PBGA (Top View) 100-Pin TQFP 1234567 A VCCQ A A ADSP A A VCCQ B NC A A ADSC A A NC C NC A A VCC A A NC D DQb NC GND NC GND DQPa NC E NC DQb GND CE GND NC DQa F VCCQ NC GND OE GND DQa VCCQ G NC DQb BWb ADV GND NC DQa H DQb NC GND GW GND DQa NC J VCCQ VCC NC VCC NC VCC VCCQ K NC DQb GND CLK GND NC DQa L DQb NC GND NC BWa DQa NC M VCCQ DQb GND BWE GND NC VCCQ N DQb NC GND A1 GND DQa NC P NC DQPb GND A0 GND NC DQa R NC A MODE VCC T NC A A NC U VCCQ TMS TDI TCK NC A TDO A NC A ZZ NC VCCQ NC NC NC VCCQ GND NC NC DQb DQb GND VCCQ DQb DQb NC VCC NC GND DQb DQb VCCQ GND DQb DQb DQPb NC GND VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VCCQ GND NC DQPa DQa DQa GND VCCQ DQa DQa GND NC VCC ZZ DQa DQa VCCQ GND DQa DQa NC NC GND VCCQ NC NC NC 1024K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock www.DatDaSQhaee-Dt4UQ.cdom Synchronous Data Input/Output DQPa-DQPb GND GW MODE OE TMS, TDI, TCK, TDO VCC VCCQ ZZ Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 Ground Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable JTAG Boundary Scan Pins +2.5V Power Supply Isolated Output Buffer Supply: +2.5V Snooze Enable Integrated Silicon Solution, Inc. — 1-800-379-4774 ADVANCE INFORMATION Rev. 00A 10/23/01 5 5 Page IS61VF51232 IS61VF51236 IS61VF10018 ISSI® READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter -7.5 Min. Max. fMAX Clock Frequency — 125 tKC Cycle Time 8.0 — tKH Clock High Pulse Width 2— tKL Clock Low Pulse Width 2— tKQ Clock Access Time — 7.5 tKQX(1) Clock High to Output Invalid 1.0 — tKQLZ(1,2) Clock High to Output Low-Z 0— tKQHZ(1,2) Clock High to Output High-Z — 4.2 tOEQ Output Enable to Output Valid — 4.2 tOELZ(1,2) Output Enable to Output Low-Z 0— tOEHZ(1,2) Output Enable to Output High-Z — 4.2 tAS Address Setup Time 1.5 — tSS Address Status Setup Time 1.5 — tWS Write Setup Time 1.5 — tCES Chip Enable Setup Time 1.5 — tAVS Address Advance Setup Time 1.5 — tAH Address Hold Time 0.5 — tSH Address Status Hold Time 0.5 — tWH Write Hold Time 0.5 — tCEH Chip Enable Hold Time 0.5 — tAVH Address Advance Hold Time 0.5 — Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. -8.5 Min. Max. — 100 10 — 2.3 — 2.3 — — 8.5 1.5 — 0— — 5.0 — 5.0 0— — 5.0 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns www.DataSheet4U.com Integrated Silicon Solution, Inc. — 1-800-379-4774 ADVANCE INFORMATION Rev. 00A 10/23/01 11 11 Page

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