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LM5035B の電気的特性と機能

LM5035BのメーカーはNational Semiconductorです、この部品の機能は「PWM Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 LM5035B
部品説明 PWM Controller
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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LM5035B Datasheet, LM5035B PDF,ピン配置, 機能
www.DataSheet4U.com
LM5035B
July 7, 2009
PWM Controller with Integrated Half-Bridge and SyncFET
Drivers
General Description
The LM5035B Half-Bridge Controller/Gate Driver contains all
of the features necessary to implement half-bridge topology
power converters using voltage mode control with line voltage
feed-forward.
The LM5035B is a functional variant of the LM5035A half-
bridge PWM controller. The LM5035B provides higher maxi-
mum duty cycle and higher start-up regulator output current
than the LM5035A or LM5035. Also, the Synchronous Recti-
fier drive outputs of the LM5035B are held low in shutdown
modes.
The LM5035, LM5035A, and LM5035B include a floating
high-side gate driver, which is capable of operating with sup-
ply voltages up to 105V. Both the high-side and low-side gate
drivers are capable of 2A peak. An internal high voltage start-
up regulator is included, along with programmable line un-
dervoltage lockout (UVLO) and overvoltage protection (OVP).
The oscillator is programmed with a single resistor to fre-
quencies up to 2MHz. The oscillator can also be synchronized
to an external clock. A current sense input and a pro-
grammable timer provide cycle-by-cycle current limit and ad-
justable hiccup mode overload protection.
Features
105V / 2A Half-Bridge Gate Drivers
Synchronous Rectifier Control Outputs with
Programmable Delays
Synchronous Rectifiers Turned Off in Shutdown Modes.
Reduced Deadtime Between High and Low Side Drive for
Higher Maximum Duty Cycle.
High Voltage (105V) Start-up Regulator
Voltage mode Control with Line Feed-Forward and Volt
Second Limiting
Resistor Programmed, 2MHz Capable Oscillator
Programmable Line Under-Voltage Lockout and Over-
Voltage Protection
Internal Thermal Shutdown Protection
Adjustable Soft-Start
Versatile Dual Mode Over-Current Protection with Hiccup
Delay Timer
Cycle-by-Cycle Over-Current Protection
Direct Opto-coupler Interface
5V Reference Output
Packages
TSSOP-20EP (Thermally enhanced)
LLP-24 (4mm x 5mm)
Simplified Application Diagram
© 2009 National Semiconductor Corporation 300913
30091301
www.national.com

1 Page





LM5035B pdf, ピン配列
wwOwr.DdateaSrhineegt4UI.ncofmormation
Order Number
LM5035BMH
LM5035BMHX
LM5035BSQ
LM5035BSQX
Package Type
TSSOP-20EP
TSSOP-20EP
LLP-24
LLP-24
NSC Package Drawing
MXA20A
MXA20A
SQA24B
SQA24B
Supplied As
73 Units per Rail
2500 Units on Tape and Reel
1000 Units on Tape and Reel
4500 Units on Tape and Reel
Pin Descriptions
TSSOP
PIN
LLP PIN
1 23
2 24
32
43
54
65
76
87
98
10 9
Name
RAMP
UVLO
OVP
COMP
RT
AGND
CS
SS
DLY
RES
Description
Application Information
Modulator ramp signal
An external RC circuit from VIN sets the ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET.
Discharge is initiated by either the internal clock or the Volt •
Second clamp comparator.
Line Under-Voltage Lockout
An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO reaches
the 0.4V threshold the VCC and REF regulators are enabled.
When UVLO reaches the 1.25V threshold, the SS pin is released
and the device enters the active mode. Hysteresis is set by an
internal current sink that pulls 23 µA from the external resistor
divider.
Line Over-Voltage Protection
An external voltage divider from the power source sets the
shutdown levels. The threshold is 1.25V. Hysteresis is set by an
internal current source that sources 23µA into the external
resistor divider.
Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources
current into an internal NPN current mirror. The PWM duty cycle
is maximum with zero input current, while 1mA reduces the duty
cycle to zero. The current mirror improves the frequency
response by reducing the AC voltage across the opto-coupler
detector.
Oscillator Frequency Control and
Sync Clock Input.
Normally biased at 2V. An external resistor connected between
RT and AGND sets the internal oscillator frequency. The internal
oscillator can be synchronized to an external clock with a
frequency higher than the free running frequency set by the RT
resistor.
Analog Ground
Connect directly to Power Ground.
Current Sense input for current
limit
If CS exceeds 0.25V the output pulse will be terminated, entering
cycle-by-cycle current limit. An internal switch holds CS low for
50ns after HO or LO switches high to blank leading edge
transients.
Soft-start Input
An internal 110 µA current source charges an external capacitor
to set the soft-start rate. During a current limit restart sequence,
the internal current source is reduced to 1.2µA to increase the
delay before retry.
Timing programming pin for the
LO and HO to SR1 and SR2
outputs.
An external resistor to ground sets the timing for the non-overlap
time of HO to SR1 and LO to SR2.
Restart Timer
If cycle-by-cycle current limit is exceeded during any cycle, a 22
µA current is sourced to the RES pin capacitor. If the RES
capacitor voltage reaches 2.5V, the soft-start capacitor will be
fully discharged and then released with a pull-up current of 1.2µA.
After the first output pulse at LO (when SS > COMP offset,
typically 1V), the SS pin charging current will revert to 110 µA.
3 www.national.com


3Pages


LM5035B 電子部品, 半導体
Symbol Parameter
www.DataSShoefte-tS4tUa.rcto(mSS Pin)
Conditions
ISS Charging current in normal
operation
VSS = 0
Charging current during a hiccup
mode restart
VSS = 0
Soft-stop Current Sink
Oscillator (RT Pin)
VSS = 2.5V
FSW1
FSW2
Frequency 1 (at HO, half oscillator
frequency)
Frequency 2 (at HO, half oscillator
frequency)
RRT = 15 k, TJ = 25°C
RRT = 15 k, TJ = -40°C to 125°C
RRT = 5.49 k
DC level
Input Sync threshold
PWM Controller (Comp Pin)
Delay to output
VPWM-OS
SS to RAMP offset
Minimum duty cycle
SS = 0V
Small signal impedance
ICOMP = 600µA, COMP current to PWM
voltage
Main Output Drivers (HO and LO Pins)
Output high voltage
Output low voltage
Rise time
Fall time
Peak source current
Peak sink current
HB Threshold
Voltage Feed-Forward (RAMP Pin)
IOUT = 50mA, VHB - VHO, VVCC - VLO
IOUT = 100 mA
CLOAD = 1 nF
CLOAD = 1 nF
VHO,LO = 0V, VVCC = 10V
VHO,LO = 10V, VVCC = 10V
VCC rising
RAMP comparator threshold
COMP current = 0
Synchronous Rectifier Drivers (SR1, SR2)
Output high voltage
IOUT = 10mA, VVCC - VSR1, VVCC - VSR2
Output low voltage
IOUT = 20 mA (sink)
Rise time
CLOAD = 1 nF
Fall time
CLOAD = 1 nF
Peak source current
VSR = 0, VVCC = 10V
Peak sink current
VSR = VVCC, VVCC = 10V
T1 Deadtime, SR1 falling to HO rising, RDLY = 10k
SR2 falling to LO rising
RDLY = 27.4k
RDLY = 100k
T2 Deadtime, HO falling to SR1 rising, RDLY = 10k
LO falling to SR2 rising
RDLY = 27.4k
RDLY = 100k
Min Typ Max Units
80 110 140 µA
0.6 1.2 1.8 µA
80 110 140 µA
185 200 215 kHz
180 220
430 500 570 kHz
2V
2.5 3 3.4 V
80
0.7 1 1.2
0
6200
ns
V
%
0.5 0.25
0.2 0.5
15
13
1.25
2
3.8
2.4 2.5 2.6
0.25
68
20
0.1
0.08
40
20
0.5
0.5
33
86
300
18
29
80
0.2
120
42
V
V
ns
ns
A
A
V
V
V
V
ns
ns
A
A
ns
ns
ns
ns
ns
ns
www.national.com
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
LM5035

Half-Bridge and SyncFET Drivers (Rev. H)

Texas Instruments
Texas Instruments
LM5035

PWM Controller with Integrated Half-Bridge and SyncFET Drivers

National Semiconductor
National Semiconductor
LM5035A

LM5035A/5035A-1 PWM Controller with Integrated Half-Bridge SyncFET Drivers (Rev. F)

Texas Instruments
Texas Instruments
LM5035A

PWM Controller

National Semiconductor
National Semiconductor


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