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PDF ISL6420B Data sheet ( Hoja de datos )
| Número de pieza | ISL6420B | |
| Descripción | Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
April 27, 2009
ISL6420B
FN6901.0
Advanced Single Synchronous Buck
Pulse-Width Modulation (PWM) Controller
The ISL6420B simplifies the implementation of a complete
control and protection scheme for a high-performance
DC/DC buck converter. It is designed to drive N-channel
MOSFETs in a synchronous rectified buck topology, the
ISL6420B integrates control, output adjustment, monitoring
and protection functions into a single package. Additionally,
the IC features an external reference voltage tracking mode
for externally referenced buck converter applications and
DDR termination supplies, as well as a voltage margining
mode for system testing in networking DC/DC converter
applications.
The ISL6420B provides simple, single feedback loop,
voltage mode control with fast transient response. The
output voltage of the converter can be precisely regulated to
as low as 0.6V.
The operating frequency is fully adjustable from 100kHz to
1.4MHz. High frequency operation offers cost and space
savings.
The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate that enables high converter
bandwidth for fast transient response. The PWM duty cycle
ranges from 0% to 100% in transient conditions. Selecting
the capacitor value from the ENSS pin to ground sets a fully
adjustable PWM soft-start. Pulling the ENSS pin LOW
disables the controller.
The ISL6420B monitors the output voltage and generates a
PGOOD (power good) signal when soft-start sequence is
complete and the output is within regulation. A built-in
overvoltage protection circuit prevents the output voltage
from going above typically 115% of the set point. Protection
from overcurrent conditions is provided by monitoring the
rDS(ON) of the upper MOSFET to inhibit the PWM operation
appropriately. This approach simplifies the implementation
and improves efficiency by eliminating the need for a current
sensing resistor.
Features
• Operates From:
- 4.5V to 5.5V Input
- 5.5V to 28V Input
• 0.6V Internal Reference Voltage
- ±2.0% Reference Accuracy
• Resistor-Selectable Switching Frequency
- 100kHz to 1.4MHz
• Voltage Margining and External Reference Tracking
Modes
• Output Can Sink or Source Current
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(ON)
• Programmable Soft-Start
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Extensive Circuit Protection Functions
- PGOOD, Overvoltage, Overcurrent, Shutdown
• Diode Emulation during Startup for Pre-Biased Load
Applications
• Offered in 20 Ld QFN and QSOP Packages
• QFN (4x4) Package
- QFN compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies for Microprocessors/ASICs
- Embedded Controllers
- DSP and Core Processors
- DDR SDRAM Bus Termination
• Ethernet Routers and Switchers
• High-Power DC/DC Regulators
• Distributed DC/DC Power Architecture
• Personal Computer Peripherals
• Externally Referenced Buck Converters
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6420B
www.TDaytapSihceaetl4U1.2coVm Input DC/DC Application Schematic
12V
C7
C1
R2
R3
C6
C2 C3 C4
VIN PVCC
VCC5
SS/EN
RT
MONITOR AND
PROTECTION
OCSET
BOOT
CDEL
PGOOD
SGND
FB
OSC
REF
+
-
-
+
UGATE
PHASE
LGATE
PGND
C5
R1
Q1
Q2
D1
C8
L1
C9
COMP
C10
C11 R5
R4 VMSET/MODE
VCC5
GPIO1/REFIN <-- VREF = VDDQ/2
GPIO2
REFOUT
C12
1.25V VREF
TO REFIN OF VTT SUPPLY
CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS
2.5V/1.25V
VDDQ/VTT
5 FN6901.0
April 27, 2009
5 Page 
ISL6420B
www.DataSheet4U.com
TABLE 2. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION
PIN CONFIGURATIONS
FUNCTION/MODES
VMSET/MODE
REFOUT
GPIO1/REFIN
(Note 9)
GPIO2
(Note 9)
Enable Voltage Margining
Pin Connected to GND Connect a 2.2µF capacitor Serves as a general
with resistor. It is used for bypass of external
purpose I/O. Refer to
as VMSET.
reference.
Table 3.
Serves as a general
purpose I/O. Refer to
Table 3.
No Voltage Margining. Normal operation
with internal reference. Buffered
VREFOUT = 0.6V.
No Voltage Margining. External
reference. Buffered VREFOUT = VREFIN
H
Connect a 2.2µF capacitor
H (Note 10)
to GND.
H Connect a 2.2µF capacitor Connect to an external
to GND.
reference voltage source
(0.6V to 1.25V)
L
L
NOTES:
9. The GPIO1/REFIN and GPIO2 pins cannot be left floating.
10. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
GPIO1/REFIN
This is a dual function pin. If VMSET/MODE is not connected
to VCC5 then this pin serves as GPIO1. Refer to Table 3 for
GPIO commands interpretation.
If VMSET/MODE is connected to VCC5 then this pin will
serve as REFIN. As REFIN, this pin is the non-inverting input
to the error amplifier. Connect the desired reference voltage
to this pin in the range of 0.6V to 1.25V.
Connect this pin to VCC5 to use internal reference.
REFOUT
It provides buffered reference output for REFIN. Connect
2.2µF decoupling capacitor to this pin.
VMSET/MODE
This pin is a dual function pin. Tie this pin to VCC5 to disable
voltage margining. When not tied to VCC5, this pin serves as
VMSET. Connect a resistor from this pin to ground to set
delta for voltage margining. If voltage margining and external
reference tracking mode are not needed, this pin can be tied
directly to ground.
GPIO2
This is general purpose IO pin for voltage margining. Refer
to Table 3.
Exposed Thermal Pad
This pad is electrically isolated. Connect this pad to the
signal ground plane using at least five vias for a robust
thermal conduction path.
TABLE 3. VOLTAGE MARGINING CONTROLLED BY GPIO1
AND GPIO2
GPIO1
GPIO2
VOUT
L L No Change
L H +ΔVOUT
H L -ΔVOUT
H H Ignored
Functional Description
Initialization
The ISL6420B automatically initializes upon receipt of power.
The Power-On Reset (POR) function monitors the internal bias
voltage generated from LDO output (VCC5) and the ENSS pin.
The POR function initiates the soft-start operation after the
VCC5 exceeds the POR threshold. The POR function inhibits
operation with the chip disabled (ENSS pin <1V).
The device can operate from an input supply voltage of 5.6V
to 28V connected directly to the VIN pin using the internal 5V
linear regulator to bias the chip and supply the gate drivers.
For 5V ±10% applications, connect VIN to VCC5 to bypass
the linear regulator.
Soft-Start/Enable
The ISL6420B soft-start function uses an internal current
source and an external capacitor to reduce stresses and
surge current during start-up.
When the output of the internal linear regulator reaches the
POR threshold, the POR function initiates the soft-start
sequence. An internal 10µA current source charges an
external capacitor on the ENSS pin linearly from 0V to 3.3V.
When the ENSS pin voltage reaches 1V typically, the
internal 0.6V reference begins to charge following the dv/dt
of the ENSS voltage. As the soft-start pin charges from 1V to
1.6V, the reference voltage charges from 0V to 0.6V.
Figure 9 shows a typical soft-start sequence.
11 FN6901.0
April 27, 2009
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL6420B.PDF ] | |
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