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PDF NJU6434 Data sheet ( Hoja de datos )

Número de pieza NJU6434
Descripción 1/4 Duty LCD Driver
Fabricantes NJR Corporation 
Logotipo NJR Corporation Logotipo



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1/4 DUTY LCD DRIVER
NJU6434
PRELIMINARY
! GENERAL DESCRIPTION
The NJU6434 is a 1/4 duty LCD driver for segment type
LCD panel.
The LCD driver consists of 4-common and 50-segment
drives up to 200 segments.
The NJU6434 is useful for the digital tuning system or
others segment type display driver.
! PACKAGE OUTLINE
NJU6434KS4
! FEATURES
# 50 Segment Drivers
# Duty Ratio 1/4 (Up to 200-Segments)
# Serial Data Transmission (Shift Clock 2MHz max.)
# Oscillation Circuit On-chip (External Resistance Required)
# Display Off Function (INHb Terminal)
# Operating Voltage
2.4 to 5.5V
# LCD Driving Voltage
VDD to 6.0V
# Package Outline
Chip, QFN 64-S4, QFP64-H2
# C-MOS Technology
P-Sub
NJU6434C
NJU6434FH2
! BLOCK DIAGRAM
Common Driver
Latch Circuit / Segment Driver
OSC1
OSC2
VDD
VLCD
VSS
INHb
CE
DATA
MODE
SCL
Oscillation
Divider
LCD Driving
Voltage Circuit
Shift
Shift
Shift
Shift
Input Register4 Input Register3 Input Register2 Input Register1
Select 50-bit Select 50-bit Select 50-bit Select 50-bit
Reset
Circuit
Input Select Circuit
Decoder
Shift Register
Control Circuit
Ver.2009-05-08
-1-

1 page




NJU6434 pdf
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NJU6434
(2) Mode Setting
The mode setting is composed of 4-bit, and selects the shift register that writes the display data by writing
data in the mode setting register. (Refer to "(4) Data Input Timing" for details.)
When the data (1,1,1,1) is input, “0” (All Display-off) is written in all shift registers.
The mode setting register is selected by CE="H" and MODE="H". The data is latched at the rising edge of
the SCL, and selected at falling edge of the CE.
Mode
1
2
3
4
5
F
Data
(MSB) 1,0,0,0 (LSB)
0,1,0,0
1,1,0,0
0,0,1,0
1,0,1,0
1,1,1,1
Table 1. Mode Setting Table
Description
Shift register 1 is selected.
Shift register 2 is selected.
Shift register 3 is selected.
Shift register 4 is selected.
All Shift register (1~4) is selected, and data is written continuously.
All shift register is “0”.
(3) Correspondence of the transfer data and output terminal
The display data is written by CE="H" and MODE="L". The data is latched at the rising edge of the SCL, and
written at falling edge of the CE.
The correspondence of the data and the output terminals is as follows.
Output
Terminal
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
COM1
D1
D5
D9
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
COM2
D2
D6
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
COM3
D3
D7
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
COM4
D4
D8
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
Output
Terminal
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
COM1
D101
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
COM2
D102
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
COM3
D103
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
COM4
D104
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
Correspondence of the transfer data and Segment Status
Transfer Data
”H”
”L”
Segment Status
ON
OFF
Ver.2009-05-08
-5-

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NJU6434
DC Characteristics
PARAMETER
SYMBOL
CONDITIONS
Operating Voltage (1)
Operating Voltage (2)
"H" Input Voltage
"L” Input Voltage
"H" Input Current
"L" Input Current
"H" Output Voltage (1)
"L” Output Voltage (1)
Middle Level Voltage 2/3 (1)
Middle Level Voltage 1/3 (1)
"H" Output Voltage (2)
"L" Output Voltage (2)
Middle Level Voltage 2/3 (2)
Middle Level Voltage 1/3 (2)
Oscillating Frequency Range
VDD
VLCD
VIH
VIL
IIH
IIL
VOH(1)
VOL(1)
VMS2/3
VMS1/3
VOH(2)
VOL(2)
VMC2/3
VMC1/3
fosc
Oscillating Frequency
fosc
Operating Current (1)
IDD
Operating Current (2)
ILCD
Hysteresis Voltage
VH
Note 1) V1=2/3VLCD, V2=1/3VLCD
VDD Terminal
VLCD Terminal
CE, SCL, DATA, MODE, INHb
CE,SCL,
DATA,MODE,
INHb
VI=VDD
VI=VSS
SEG1~SEG50 Io=-10uA
VLCD=5V
Io=+10uA
SEG1~SEG50 Io=±10uA
Ta=25°C,
VLCD=5V
Io=±10uA
COM1~COM4 Io=-100uA
VLCD=5V
Io=+100uA
COM1~COM4
Ta=25°C,
VLCD=5V
Io=±100uA
Io=±100uA
OSC1, OSC2 Terminals
Ta=25°C
OSC1, OSC2,
R=750k
Ta=25°C
VDD Terminal, Ta=25°C
VLCD Terminal, Ta=25°C
CE, SCL, DATA, MODE, INHb
(VDD=4.5~5.5V, VLCD=VDD, Ta=-40~+85°C)
MIN
4.5
VDD
0.7VDD
VSS
TYP
5.0
MAX
5.5
6
VDD
0.3VDD
1
UNIT
V
V
V
V
uA
NO
TE
1 uA
VLCD-0.4
VSS
V1-0.4
V2-0.4
V1
V2
VLCD V
0.4 V
V1+0.4 V
V2+0.4 V 1
VLCD-0.5
VSS
V1-0.5.
V2-0.5
V1
V2
VLCD V
0.5 V
V1+0.5 V
V2+0.5 V 1
10 20 kHz
12.6 15.4 18.2 kHz
25
15
0.3
50 uA
30 uA
V
VLCD
V1 2/3VLCD
V2 1/3VLCD
VSS
Ver.2009-05-08
- 11 -

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