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PDF ISL59922 Data sheet ( Hoja de datos )

Número de pieza ISL59922
Descripción (ISL59921 - ISL59923) Triple Analog Video Delay Lines
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL59922 Hoja de datos, Descripción, Manual

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ISL59920, ISL59921, ISL59922, ISL59923
®
Data Sheet
May 28, 2009
FN6826.1
Triple Analog Video Delay Lines
The ISL59920, ISL59921, ISL59922, and ISL59923 are
triple analog delay lines that provide skew compensation
between three high-speed signals. These parts are ideal for
compensating for the skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable (with differing electrical lengths on
each twisted pair) when transmitting analog video.
Using a simple serial interface, the ISL59920, ISL59921,
ISL59922, and ISL59923’s delays are programmable in
steps of 2, 1.5, 1, or 2ns (respectively) for up to a total delay
of 62, 46.5, 31, or 30ns (respectively) on each channel. The
gain of the video amplifiers can be set to x1 (0dB) or x2
(6dB) for back-termination. The delay lines require a ±5V
supply.
Features
• 30, 31, 46.5, or 62ns Total Delay
• 1.0, 1.5, or 2.0ns Delay Step Increments
• Very Low Offset Voltage
• Drop-in Compatible with the EL9115
• Low Power Consumption
• 20 Ld QFN Package
• Pb-Free (RoHS Compliant)
Applications
• Skew Control for RGB Video Signals
• Generating Programmable High-speed Analog Delays
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
MAX
DELAY
(ns)
DELAY
STEP
SIZE
(ns)
TYPICAL
POWER
DISSIPATION
(mW)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL59920IRZ*
59920 IRZ
62 2.0
645 20 Ld 5mmx5mm QFN
L20.5x5C
ISL59921IRZ*
59921 IRZ
46.5 1.5
645 20 Ld 5mmx5mm QFN
L20.5x5C
ISL59922IRZ*
59922 IRZ
31 1.0
645 20 Ld 5mmx5mm QFN
L20.5x5C
ISL59923IRZ*
59923 IRZ
30 2.0
540 20 Ld 5mmx5mm QFN
L20.5x5C
*Add “-T7” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinout
ISL59920, ISL59921, ISL59922, ISL59923
(20 LD 5X5 QFN)
TOP VIEW
VSP 1
RIN 2
GND 3
GIN 4
VSM 5
THERMAL
PAD
15 ROUT
14 GNDO
13 GOUT
12 VSMO
11 BOUT
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL59922 pdf
ISL59920, ISL59921, ISL59922, ISL59923
www.PDaitnaSDheeets4Uc.rcoipmtions
PIN NUMBER
PIN NAME
1 VSP
2 RIN
3 GND
4 GIN
5 VSM
6 BIN
7 CENABLE
8 SENABLE
9 SDATA
10 SCLOCK
11 BOUT
12 VSMO
13 GOUT
14 GNDO
15 ROUT
16 VSPO
17 TESTB
18 TESTG
19 TESTR
20 X2
Thermal Pad
PIN DESCRIPTION
+5V for delay circuitry and input amp
Red channel video input
0V for delay circuitry supply
Green channel video input
-5V for input amp
Blue channel video input
Chip Enable input, active high: logical high enables chip, low disables chip
Serial Enable input, active low: logical low enables serial communication
Serial Data input, logic threshold 1.2V: data to be programmed into chip
Serial Clock input: Clock to enter data; logical; data written on negative edge
Blue channel video output
-5V for video output buffers
Green channel video output
0V reference for input and output buffers
Red channel video output
+5V for video output buffers
Blue channel phase detector output
Green channel phase detector output
Red channel phase detector output
Gain Select Input: logical high = 2x (+6dB), logical low = 1x (0dB)
MUST be tied to -5V. For best thermal conductivity also tie to a larger -5V copper plane (inner
or bottom). Use many vias to minimize thermal resistance between thermal pad and copper
plane. Do not connect to GND - connection to GND is equivalent to shorting the -5V and GND
planes together.
5 FN6826.1
May 28, 2009

5 Page





ISL59922 arduino
ISL59920, ISL59921, ISL59922, ISL59923
www.TDaytapSihceaetl4UP.ceormformance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
4.5
4.0 3.54W
3.5
3.0
2.5
θJA =Q31F°NC2/0W
2.0
1.5
1.0
0.5
0
0
25 50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
1
2 RIN +
19 17 18
DELAY LINE
16
CENABLE 7
+ ROUT 15
4 GIN +
6 BIN +
9 SDATA
10 SCLOCK
8 SENABLE
DELAY LINE
DELAY LINE
CONTROL LOGIC
+ GOUT 13
+ BOUT 11
X2 20
[BOTTOM PLATE]
35
C 12 14
FIGURE 33. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM
Applications Information
The ISL59920, ISL59921, ISL59922, and ISL59923 are
triple analog delay lines that provide skew compensation
between three high-speed signals. These devices
compensate for time skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable with differing electrical lengths (due to
different twist ratios) on each pair. Via their SPI interface,
these devices can be programmed to independently
compensate for the three different cable delays while
maintaining 80MHz bandwidth at their maximum setting.
There are four different variations of the ISL5992x (ISL5992x
will be used when talking about characteristics that are
common to all four devices).
PART NUMBER
ISL59920
ISL59921
ISL59922
ISL59923
TABLE 1.
MAX DELAY
(ns)
62
46.5
31
30
NOMINAL DELAY
INCREMENT
(ns)
2.0
1.5
1.0
2.0
11 FN6826.1
May 28, 2009

11 Page







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