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PI2EQX3231BL の電気的特性と機能

PI2EQX3231BLのメーカーはPericom Semiconductor Corporationです、この部品の機能は「1-port SATA2 I/m ReDriver」です。


製品の詳細 ( Datasheet PDF )

部品番号 PI2EQX3231BL
部品説明 1-port SATA2 I/m ReDriver
メーカ Pericom Semiconductor Corporation
ロゴ Pericom Semiconductor Corporation ロゴ 




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PI2EQX3231BL Datasheet, PI2EQX3231BL PDF,ピン配置, 機能
www.DataSheet4U.com
Features
• SATA2 i, m; external SATA2
• Two 3.0Gbps differential signal pairs
• Adjustable Receiver Equalization
• 100-Ohm Differential CML I/O’s
• Independent Output Emphasis Control
• Input signal level detect and squelch for each channel
• OOB Support
• Low Power (100mW per Channel)
• Stand-by Mode – Power Down State
• VDD Operating Range: 1.5V to 1.8V
• Packaging: — 20-TQFN (3.5x 4.5mm)
PI2EQX3231BL
3.0Gbps, 1-port, SATA2 i/m Re-Driver
Description
Pericom Semiconductor’s PI2EQX3231BL is a low power,
signal Re-Driver. The device provides programmable
equalization, to optimize performance over a variety of
physical mediums by reducing Inter-Symbol Interference.
PI2EQX3231BL supports two 100-Ohm Differential CML data
I/O’s between the Protocol ASIC to a switch fabric, across a
backplane, or to extend the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides exibility with
signal integrity of the signal before the re-driver.
A low-level input signal detection and output squelch function
is provided for each channel. Each channel operates fully
independantly. When the channels are enabled (CE=1) and
operating, that channels input signal level (on xI+/-) determines
whether the output is active. If the input signal level of the channel
falls below the active threshold level (Vth-) then the outputs are
driven to the common mode voltage.
In addition to signal conditioning, when CE = 0, the device
enters a low power standby mode.
Block Diagram
Signal Detection
CML
XI+
XI
x_EQ
CE
Equalizer
Limiting
Amp
- Repeated 2 times -
Power
Management
Pin Diagram (Top Side View)
CML
XO+
XO
x_EM
VDD
AI+
AI-
GND
VDD
BO+
BO-
VDD
1 20
2 19
3 18
4 17
5
GND
16
6 15
7 14
8 13
9 12
10 11
CE
AO+
AO-
GND
VDD
BI+
BI-
GND
08-0328
1
PS8997B
12/04/08

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PI2EQX3231BL pdf, ピン配列
www.DataSheet4U.com
PI2EQX3231BL
3.0Gbps, 1-Port, SATA2 i/m Re-Driver
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................ –65°C to +150°C
Supply Voltage to Ground Potential ................................... –0.5V to +2.5V
DC SIG Voltage..........................................................–0.5V to VDD +0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous ......................................................... 500mW
Operating Temperature.............................................................. 0 to +70°C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specication is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
AC/DC Electrical Characteristics (VDD = 1.4V to 1.9V)
Symbol
Parameter
Conditions
Min. Typ. Max. Units
IDD Power Supply Current
90 mA
Pstandby
Pactive18
Power, standby
Power, active @ 1.8V
EN_[A:B] = 0
VDD=1.8V, EN_[A:B] = 1, Vrx-diff-p >= Vth-sd
125
1
160
mW
Pidle18
Power, idle @ 1.8V
VDD=1.8V, EN_[A:B] = 1, Vrx-diff-p < Vth-sd
100
mW
Pactive15
Pidle15
tpd
Power, active @ 1.5V
Power, idle @ 1.5V
Latency
VDD=1.5V, EN_[A:B] = 1, Vrx-diff-p >= Vth-sd
VDD=1.5V, EN_[A:B] = 1, Vrx-diff-p < Vth-sd
From differential input to differential output
100 130 mW
80 mW
2.0 ns
CML Receiver Input
VRX-DIFFP-P
Differential Input Peak-to-
peak Voltage
VRX-CM-ACP
AC Peak Common Mode
Input Voltage
VTH-SD
Signal detect Threshold
ZRX-DC
DC Input Impedance
ZRX-DIFF-DC
DC Differential Input
Impedance
CE = 1
0.200
V
50(2)
40
80
150 mV
200 (3) mVppd
50 60
100 120 Ohm
Equalization
JRS Residual Jitter(1,2)
JRM Random Jitter(1,2)
Total Jitter
0.3 Ulp-p
1.5 psrms
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at
0V at point C of Figure 1.
3. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The
ALIGN primitive (K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011
08-0328
3
PS8997B
12/04/08


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部品番号部品説明メーカ
PI2EQX3231BL

1-port SATA2 I/m ReDriver

Pericom Semiconductor Corporation
Pericom Semiconductor Corporation


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