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PDF ispPAC-POWR605 Data sheet ( Hoja de datos )
| Número de pieza | ispPAC-POWR605 | |
| Descripción | In-System Programmable Power Supply Supervisor | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ProcessorPMT-M POWR605
In-System Programmable Power Supply Supervisor,
Reset Generator and Watchdog Timer
April 2009
Preliminary Data Sheet DS1034
Features
■ Precision Programmable Threshold
Monitors, Threshold Accuracy 0.7%
• Simultaneously monitors up to six power supplies
• Programmable analog trip points (1% step size;
192 steps)
• Programmable glitch filter
• Power-off detection (75mV)
■ Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
■ Embedded PLD for Logical Control
• Rugged 16-macrocell CPLD architecture
• 81 product terms / 28 inputs
• Implements state machines and combinatorial
functions
■ Power-Down Mode ICC < 10µA
■ Digital I/O
• Two dedicated digital inputs
• Five programmable digital I/O pins
■ Wide Supply Range (2.64V to 3.96V)
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 24-pin QFN package, lead-free option
Description
Lattice’s Power Manager II ProcessorPM-POWR605 is
a general-purpose power-supply monitor, reset genera-
tor and watchdog timer, incorporating both in-system
programmable logic and analog functions implemented
in non-volatile E2CMOS® technology. The ProcessorPM-
POWR605 device provides six independent analog
input channels to monitor power supply voltages. Two
general-purpose digital inputs are also provided for mis-
cellaneous control functions.
The ProcessorPM-POWR605 provides up to five open
drain digital outputs that can be used for controlling DC-
DC converters, low-drop-out regulators (LDOs) and
optocouplers, as well as for supervisory and general-
purpose logic interface functions. The five digital, open
drain outputs can optionally be configured as digital
inputs to sense more input signals as needed, such as
manual reset, etc.
Application Block Diagram
Input Power Supply
Manual
Reset In
DC-DC DC-DC
#1 #2
Power
Supply
Bus
DC-DC
#n
Voltage Supervisor
Reset Generator
Interrupt –
Power Fail
CPU_Reset_in
Watchdog Timer
WDT Trigger
Interrupt – WDT
Power Down
ProcessorPM-
POWR605
CPU /
uProcessor
Power Up/Down Control
The diagram above shows how a ProcessorPM-
POWR605 is used in a typical application. It controls
power to the microprocessor system, generates the
CPU reset and monitors critical power supply voltages,
generating interrupts whenever faults are detected. It
also provides a watchdog timer function to detect CPU
operating and bus timeout errors.
The ProcessorPM-POWR605 incorporates a 16-macro-
cell CPLD. Figure 1 shows the analog input compara-
tors and digital inputs used as inputs to the CPLD array.
The digital output pins providing the external control sig-
nals are driven by the CPLD. Four independently pro-
grammable timers also interface with the CPLD and can
create delays and time-outs ranging from 32µs to 2 sec-
onds. The CPLD is programmed using LogiBuilder™,
an easy-to-learn language integrated into the PAC-
Designer® software. Control sequences are written to
monitor the status of any of the analog input channel
comparators or the digital inputs.
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
1
DS1034_01.0
1 page  
www.DaLtaaSthteicete4US.coemmiconductor
ProcessorPM-POWR605 Data Sheet
Voltage Monitors
Symbol
Parameter
Conditions
RIN
CIN
VMON Range
VZ Sense
VMON Accuracy
Input resistance
Input capacitance
Programmable trip-point range
Near-ground sense threshold
25°C,
trip point <2.7V
Absolute accuracy of any trip-point1
25°C,
trip point >2.7V
TEMPCO_THRESHOLD Threshold temperature coefficient
HYST
Hysteresis of any trip-point (relative
to setting)
1. Guaranteed by characterization across VCC range, operating temperature, process.
Min.
55
0.075
70
Typ.
65
8
75
60
1
Max.
75
5.793
80
0.7
0.8
Units
kΩ
pF
V
mV
%
%
ppm/c
%
VMON Trip Point Accuracy: Thresholds ≤2.7V
3000
2500
2000
1500
1000
500
0
Trip Point Error (%)
Threshold setting accuracy histogram for all trip points ≤2.7V.
VMON Trip Point Accuracy: Thresholds >2.7V
350
300
250
200
150
100
50
0
Trip Point Error (%)
Threshold setting accuracy histogram for all trip points >2.7V.
5
5 Page 
www.DaLtaaSthteicete4US.coemmiconductor
ProcessorPM-POWR605 Data Sheet
Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal (VMONx pin) is
greater than its programmed trip point setting, otherwise it outputs a LOW signal.
A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a
result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 3
lists the typical hysteresis versus voltage monitor trip-point.
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 10 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the
comparator outputs change state at different thresholds depending on the direction of excursion of the monitored
power supply.
Figure 10. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator
Output, (b) Corresponding to Upper and Lower Trip Points
UTP
LTP
(a)
Comparator Logic Output
(b)
During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage
crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when
the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP
should be used. To monitor under-voltage fault conditions, the LTP should be used.
Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft-
ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ispPAC-POWR605.PDF ] | |
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