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PDF ISL6324A Data sheet ( Hoja de datos )
| Número de pieza | ISL6324A | |
| Descripción | Hybrid SVI/PVI | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL6324A
Hybrid SVI/PVI with I2C
March 23, 2009
FN6880.0
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6324A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6324A supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6324A features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is provided
by a 2-to-4-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers, adding flexibility in
layout, reduce the number of external components in the multi-
phase section. A single phase PWM controller with integrated
driver provides a second precision voltage regulation system
for the North Bridge portion of the processor. This monolithic,
dual controller with integrated driver solution provides a cost
and space saving power management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6324A features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient response
to load application and removal. One of these features is
highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6324A supports Power Savings Mode by dropping
phases when the PSI_L bit is set. The number of phases
that the ISL6324A will drop to is programmable through an
I2C interface. The number of PWM cycles between both
dropping phases when entering Power Savings Mode and
adding phases when exiting Power Savings Mode is also
programmable through the I2C interface.
The ISL6324A I2C interface also allows independent
programmable output voltage offset for both the Core and
North Bridge regulators. The I2C interface can also be used
to set the PGOOD and OVP trip levels for both regulators as
well.
Features
Processor Core Voltage Regulator Features
• Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• Parallel VID (6-bit) Interface Inputs for PVI Mode
• PSI_L Support via Phase Shedding
• Differential Remote Voltage Sensing
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
Processor Core Voltage Regulator and North Bridge
Voltage Regulator Shared Features
• Precision Voltage Regulation: ±0.5% System Accuracy
Over-Temperature
• Two Wire, AMD Compliant Serial VID Interface Inputs for
SVI Mode
• I2C Interface
- Voltage Margining, OVP and PGOOD Trip Levels
- Enhanced PSI_L State Control
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing for Core
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6324ACRZ* ISL6324A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6324AIRZ* ISL6324A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
www.TDaytapSihceaetl4UA.cpomplication - PVI Mode
ISL6324A
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
LGATE1
ISEN1-
+5V
DVC
ISEN1+
VCC
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VID0
VID1/SEL
VID2
ISEN2-
ISEN2+
VID3
VID4
RGND
VID5
NC PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
SCL
SDA
PWM4
ISL6324A
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614 +12V
VCC
BOOT2 PVCC
UGATE2GND
PHASE2
PWM2
LGATE2
NORTH BRIDGE REGULATOR
DISABLED IN PVI MODE
VDDNB
NB
LOAD
5 FN6880.0
March 23, 2009
5 Page 
ISL6324A
www.ODaptaeShreaett4ioU.ncom
The ISL6324A utilizes a multi-phase architecture to provide
a low cost, space saving power conversion solution for the
processor core voltage. The controller also implements a
simple single phase architecture to provide the Northbridge
voltage on the same chip.
Multi-phase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multi-phase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter that is
both cost-effective and thermally viable have forced a
change to the cost-saving approach of multi-phase. The
ISL6324A controller helps simplify implementation by
integrating vital functions and requiring minimal external
components. The “Controller Block Diagram” on page 3
provides a top level view of the multi-phase power
conversion using the ISL6324A controller.
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out-of-phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has a
combined ripple frequency three times greater than the ripple
frequency of any one phase. In addition, the peak-to-peak
amplitude of the combined inductor currents is reduced in
proportion to the number of phases (Equations 2 and 3).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine Equation 2, which represents
an individual channel peak-to-peak inductor current.
IP – P =
(---V----I--N-----–-----V----O-----U----T---)----V----O----U-----T-
L fS VIN
(EQ. 2)
In Equation 2, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 2 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 3. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
IC(P – P)=
(---V----I--N-----–-----N------V----O-----U----T---)----V----O----U-----T-
L
fS
V
IN
(EQ. 3)
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
11.9ARMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
Figures 26, 27 and 28 in the section entitled “Input Capacitor
Selection” on page 35 can be used to determine the input
capacitor RMS current based on load current, duty cycle,
and the number of channels. They are provided as aids in
determining the optimal input capacitor solution.
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
IL1, 7A/DIV
PWM2, 5V/DIV
PWM1, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
11 FN6880.0
March 23, 2009
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL6324A.PDF ] | |
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