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ISL62882B の電気的特性と機能

ISL62882BのメーカーはIntersil Corporationです、この部品の機能は「Multiphase PWM Regulator」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL62882B
部品説明 Multiphase PWM Regulator
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL62882B Datasheet, ISL62882B PDF,ピン配置, 機能
Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs
and GPUs
ISL62882, ISL62882B
The ISL62882 is a multiphase PWM buck regulator for
miroprocessor or graphics processor core power supply. The
multiphase buck converter uses interleaved phases to reduce the
total output voltage ripple with each phase carrying a portion of the
total load current, providing better system performance, superior
thermal management, lower component cost, reduced power
dissipation, and smaller implementation area. The ISL62882 uses
two integrated gate drivers to provide a complete solution. The PWM
modulator is based on Intersil's Robust Ripple Regulator (R3)
technology™. Compared with traditional modulators, the R3
modulator commands variable switching frequency during load
transients, achieving faster transient response. With the same
modulator, the switching frequency is reduced at light load,
increasing the regulator efficiency.
The ISL62882 can be configured as CPU or graphics Vcore controller
and is fully compliant with IMVP-6.5™ specifications. It responds to
PSI# and DPRSLPVR signals by adding or dropping Phase 2,
adjusting overcurrent protection threshold accordingly, and
entering/exiting diode emulation mode. It reports the regulator
output current through the IMON pin. It senses the current by using
either discrete resistor or inductor DCR whose variation over
temperature can be thermally compensated by a single NTC
thermistor. It uses differential remote voltage sensing to accurately
regulate the processor die voltage. The unique split LGATE function
further increases light load efficiency. The adaptive body diode
conduction time reduction function minimizes the body diode
conduction loss in diode emulation mode. User-selectable overshoot
reduction function offers an option to aggressively reduce the output
capacitors as well as the option to disable it for users concerned
about increased system thermal stress. The ISL62882 offers the
FB2 function to optimize 1-phase performance.
The ISL62882B has the same functions as the ISL62882, but
comes in a different package.
Features
• Programmable 1- or 2-Phase CPU Mode Operation or 1-Phase
GPU Mode Operation
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Supports PSI# and DPRSLPVR modes
• Superior Noise Immunity and Transient Response
• Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1- or 2-Phase Operation
• Two Integrated Gate Drivers
• Excellent Dynamic Current Balance Between Phases
• Split LGATE1 Drivers Increases Light Load Efficiency
• FB2 Function Optimizes 1-Phase Mode Performance
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN Packages
• Pb-Free (RoHS Compliant)
Applications
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator
June 21, 2011
FN6890.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL62882B pdf, ピン配列
ISL62882, ISL62882B
Functional Pin Descriptions
ISL62882
-
1
ISL62882B
7
2
23
34
45
56
68
79
8 10
9 11
10
11
12
13
14, 15
16
17
18
19
13
14
15
16
17, 18
19
20
22
24
20 25
21 26
22 27
23 28
24 29
--
SYMBOL
GND
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
FB2
ISEN2
ISEN1
VSEN
RTN
ISUM- and ISUM+
VDD
VIN
IMON
BOOT1
UGATE1
PHASE1
VSSP1
LGATE1a
LGATE1b
LGATE1
DESCRIPTION
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
Power-Good open-drain output indicating when the regulator is able to supply regulated voltage.
Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
Low load current indicator input. When asserted low, indicates a reduced load current condition.
A resistor to GND sets internal current reference. Use 147kΩ or 47kΩ. The choice of Rbias value,
together with the ISEN2 pin configuration and the external resistance from the COMP pin to GND,
programs the controller to enable/disable the overshoot reduction function and to select the
CPU/GPU mode.
Thermal overload output indicator.
Thermistor input to VR_TT# circuit.
A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately
300kHz).
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the
overcurrent threshold.
This pin is the inverting input of the error amplifier.
There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is
off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation
in 1-phase mode to achieve optimum performance.
Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will
disable Phase 2.
Individual current sensing for phase 1.
Remote core voltage sense input. Connect to microprocessor die.
Remote voltage sensing return. Connect to ground at microprocessor die.
Droop current sense input.
5V bias power.
Battery supply voltage, used for feed-forward.
An analog output. IMON outputs a current proportional to the regulator output current.
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each
time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the
Phase-1 high-side MOSFET.
Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.
Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the
source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1
low-side MOSFETs.
Output of the Phase-1 low-side MOSFET gate driver that is always active. Connect the LGATE1a
pin to the gate of the Phase-1 low-side MOSFET that is active all the time.
Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will be pulled low
when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to the gate of the Phase-1
low-side MOSFET that is idle in deeper sleep mode.
Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
3 FN6890.4
June 21, 2011


3Pages


ISL62882B 電子部品, 半導体
ISL62882, ISL62882B
Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE1a and 1b and LGATE2 Voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
LGATE1a and 1b
. . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 2.5µJ) to VDD+0.3V
LGATE1a and 1b
. . . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT#,
CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
40 Ld TQFN Package (Notes 4, 5) . . . . . . .
32
3
48 Ld TQFN Package (Notes 4, 5) . . . . . . .
29
2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V
Ambient Temperature
ISL62882HRTZ, ISL62882BHRTZ . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL62882IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
ISL62882HRTZ, ISL62882BHRTZ . . . . . . . . . . . . . . . . .-10°C to +125°C
ISL62882IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
4 4.6 mA
1 µA
Battery Supply Current
VIN Input Resistance
Power-On-Reset Threshold
SYSTEM AND REFERENCES
IVIN
RVIN
PORr
PORf
VR_ON = 0V
VR_ON = 3.3V
VDD rising
VDD falling
4.00
900
4.35
4.15
1
4.5
µA
kΩ
V
V
System Accuracy
HRTZ
No load; closed loop, active mode range
%Error (VCC_CORE) VID = 0.75V to 1.50V,
VID = 0.5V to 0.7375V
-0.5
-8
+0.5
+8
%
mV
VID = 0.3V to 0.4875V
-15 +15 mV
IRTZ
No load; closed loop, active mode range
%Error (VCC_CORE) VID = 0.75V to 1.50V
VID = 0.5V to 0.7375V
-0.8
-10
+0.8
+10
%
mV
VID = 0.3V to 0.4875V
-18 +18 mV
VBOOT
Maximum Output Voltage
Minimum Output Voltage
RBIAS Voltage
VCC_CORE(max)
VCC_CORE(min)
VID = [0000000]
VID = [1100000]
RBIAS = 147kΩ
1.0945
1.45
1.100
1.500
0.300
1.47
1.1055
1.49
V
V
V
V
6 FN6890.4
June 21, 2011

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共有リンク

Link :


部品番号部品説明メーカ
ISL62882

Multiphase PWM Regulator

Intersil Corporation
Intersil Corporation
ISL62882B

Multiphase PWM Regulator

Intersil Corporation
Intersil Corporation
ISL62882C

Multiphase PWM Regulator

Intersil Corporation
Intersil Corporation


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