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IP1001LF の電気的特性と機能

IP1001LFのメーカーはIC Plusです、この部品の機能は「Integrated 10/100/1000 Gigabit Ethernet Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 IP1001LF
部品説明 Integrated 10/100/1000 Gigabit Ethernet Transceiver
メーカ IC Plus
ロゴ IC Plus ロゴ 




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IP1001LF Datasheet, IP1001LF PDF,ピン配置, 機能
www.DataSheet4U.com
IP1001 LF
Data Sheet
Integrated 10/100/1000 Gigabit Ethernet Transceiver
Features
IEEE 802.3 compliant 1000BASE-T,
100BASE-TX, and 10BASE-T
Support auto-negotiation
Support timing programmable MII/ GMII/
RGMII (delay clock, and driving current etc.)
Support 3 power saving modes
Support software based Smart Cable Analyzer
(SCA)
Support auto MDI/MDIX (auto negotiation or
force mode)
Support auto polarity correction
Supports programmable LED modes and LED
driving current
Supports speed down shift feature
Built in synchronization FIFO to support jumbo
frame size up to 10KB in giga mode (4KB in
10M/100M mode)
Supports 2.1v and 1.2v built-in regulator
control
Provide a 125MHz free running clock
Operating voltage 3.3v/ (2.5v option for
RGMII)/ 1.8v/ 1.2v
64-pin QFN lead-free package
Supports Lead Free package (Please refer to
the Order Information)
General Description
IP1001 is an integrated physical layer device for
1000BASE-T, 100BASE-TX, and 10BASE-T
applications. IP1001 supports MII, GMII and
RGMII for different types of 10/100/1000Mb Media
Access Controller (MAC). It supports Auto
MDI/MDIX function to simplify the network
installation and reduce the system maintenance
cost. IP1001 supports speed down shift feature for
a poor link quality to guarantee data transmission.
Cable analysis function “SCA” is supported by
programming MII registers of IP1001 through
MDC/MDIO.
IP1001 supports 2 types of power saving modes;
i.e., power down mode defined in IEEE802.3, and
APS (auto power saving).
MAC Device
Physical Layer Device
Network Medium
SNwSNIiwCtcIiC/thc/h
RGMII/ GMII/ MII
IPI1P0100101
TP-MDI
Magnetic
Magnetic
10BASE-T
RJ45
RJ45
100BASE-TX
1000BASE-T
Copyright © 2006, IC Plus Corp.
1/48
Dec. 18, 2007
IP1001-DS-R06

1 Page





IP1001LF pdf, ピン配列
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IP1001 LF
Data Sheet
Revision History
Revision #
IP1001-DS-R01
IP1001-DS-R02
IP1001-DS-R03
IP1001-DS-R04
IP1001-DS-R05
IP1001-DS-R06
Change Description
Initial release.
Assign pin number to power pins. Modify CAP pin description. Modify package
dimension.
Modify features description. Modify the pin desecration for X1. Change the part
number to “IP1001 LF”. Modify the LED pins description. Modify the RGMII/GMII
driving current. Modify the operating temperature range. Modify RGMII/GMII timing.
Modify LED mode description of pin 55. Modify DC characteristics. Add thermal
parameters.
Correct an editing error found on Page 4.
Modify Maximum voltage of AVDD to 2.2V on Page 42 DC. Characteristic.
Copyright © 2006, IC Plus Corp.
3/48
Dec. 18, 2007
IP1001-DS-R06


3Pages


IP1001LF 電子部品, 半導体
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Pin description (continued)
IP1001 LF
Data Sheet
Pin no.
Label
Type
Configuration
50,51,53,7,8 PHY_ADDR[4:0] LI/O,
IPH
36 RGMII_N/GMII IPL
Description
PHY Address Configuration
These pins are latched upon power-on reset to define the
PHY address of IP1001.
PHY_ADDR[1:0] are internally pulled high.
PHY_ADDR[4:0] share the same pins with RXD6, RXD7,
RX_ER, CRS and COL.
GMII (MII)/ RGMII MAC Interface Mode Selection
This pin is latched upon power-on reset to define the
RGMII/GMII interface mode.
0: RGMII mode (default)
1: GMII/MII mode
48 RXPHASE_SEL LI/O RX_CLK Phase Selection
This pin is latched upon power-on reset, and acts as the initial
value of register16 [0] to adjust timing of RX_CLK.
0: No output delay is added on RX_CLK
1: An output delay is added on RX_CLK (with respect to RXD,
about 2ns delay in 1000BASE-T, and about 4ns delay in
100BASE-TX and 10BASE-T).
RXPHASE_SEL shares the same pin with RXD4.
49 TXPHASE_SEL LI/O GTX_CLK/TXC Phase Selection
This pin is latched upon power-on reset, and acts as the initial
value of register16 [1] to adjust timing of GTX_CLK/TXC.
0: No input delay is added on GTX_CLK/TXC
1: An input delay is added on GTX_CLK/TXC (with respect to
TXD, about 2ns delay in 1000BASE-T, and about 4ns
delay in 100BASE-TX and 10BASE-T).
TXPHASE_SEL shares the same pin with RXD5.
Copyright © 2006, IC Plus Corp.
6/48
Dec. 18, 2007
IP1001-DS-R06

6 Page



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部品番号部品説明メーカ
IP1001LF

Integrated 10/100/1000 Gigabit Ethernet Transceiver

IC Plus
IC Plus


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