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74HCT02 の電気的特性と機能

74HCT02のメーカーはNXP Semiconductorsです、この部品の機能は「Quad 2-input NOR gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HCT02
部品説明 Quad 2-input NOR gate
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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74HCT02 Datasheet, 74HCT02 PDF,ピン配置, 機能
74HC02; 74HCT02
Quad 2-input NOR gate
Rev. 5 — 26 November 2015
Product data sheet
1. General description
The 74HC02; 74HCT02 is a quad 2-input NOR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Input levels:
For 74HC02: CMOS level
For 74HCT02: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74HC02D
40 C to +125 C
74HCT02D
74HC02DB 40 C to +125 C
74HCT02DB
74HC02PW 40 C to +125 C
74HCT02PW
74HC02BQ 40 C to +125 C
74HCT02BQ
Name
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads; body width
3.9 mm
Version
SOT108-1
plastic shrink small outline package; 14 leads; body SOT337-1
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm

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74HCT02 pdf, ピン配列
NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
6. Functional description
Table 3.
Input
nA
L
X
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
nB
L
H
X
Output
nY
H
L
L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
SO14, (T)SSOP14 and DHVQFN14
packages
0.5
[1] -
[1] -
-
-
50
65
[2] -
+7
20
20
25
50
-
+150
500
V
mA
mA
mA
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
74HC02
Min Typ Max
2.0 5.0 6.0
0 - VCC
0 - VCC
40 - +125
- - 625
- 1.67 139
- - 83
74HCT02
Min Typ Max
4.5 5.0 5.5
0 - VCC
0 - VCC
40 - +125
---
- 1.67 139
---
Unit
V
V
V
C
ns/V
ns/V
ns/V
74HC_HCT02
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 26 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 15


3Pages


74HCT02 電子部品, 半導体
NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
Conditions
Min
74HCT02
tpd propagation delay nA, nB to nY; see Figure 6
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
CPD power dissipation per package;
capacitance
VI = GND to VCC 1.5 V
[1]
[2]
[3]
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
-
-
-
-
25 C
Typ
11
9
7
24
40 C to +125 C Unit
Max Max
Max
(85 C) (125 C)
19 24
--
15 19
--
29 ns
- ns
22 ns
- pF
11. Waveforms
9,
Q$Q%LQSXW
*1'
92+
Q<RXWSXW
92/
90
W3+/
9<
W7+/
90
9;
W3/+
W7/+
Fig 6.
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Input to output propagation delays
DDL
Table 8. Measurement points
Type
Input
VM
74HC02
0.5VCC
74HCT02
1.3 V
Output
VM
0.5VCC
1.3 V
VX
0.1VCC
0.1VCC
VY
0.9VCC
0.9VCC
74HC_HCT02
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 26 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 15

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共有リンク

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