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PDF ISL34321 Data sheet ( Hoja de datos )
| Número de pieza | ISL34321 | |
| Descripción | 16-Bit Long-Reach Video SERDES | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
March 16, 2009
ISL34321
FN6870.0
16-Bit Long-Reach Video SERDES with
Bidirectional Side-Channel
The ISL34321 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed
differential signal. This differential signal is converted back to
parallel video at the remote end by the deserializer. It also
transports auxiliary data bidirectionally over the same link
during the video vertical retrace interval.
I2C bus mastering allows the placement of external slave
devices on the remote side of the link. An I2C controller can
be place on either side of the link allowing bidirectional I2C
communication through the link to the external devices on
the other side. Both chips can be fully configured from a
single controller or independently by local controllers.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL34321INZ* ISL34321INZ -40 to +85 48 Ld EPTQFP Q48.7x7B
*Add “-T13” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• 16-bit RGB transport over single differential pair
• 6MHz to 45MHz pixel clock rates
• Bi-directional auxiliary data transport without extra
bandwidth and over the same differential pair
• Hot plugging with automatic resynchronization every
HSYNC.
• I2C Bus Mastering to the remote side of the link with a
controller on either the serializer or deserializer
• Selectable clock edge for parallel data output
• Internal 100Ω termination on high-speed serial lines
• DC balanced with industry standard 8b/10b line code
allows AC-coupling
- Provides immunity against ground shifts
• 16 programmable settings each for transmitter amplitude
boost and pre-emphasis and receiver equalization allow
for longer cable lengths and higher data rates
• Programmable powerdown of the transmitter and the
receiver.
• Same device for serializer and deserializer simplifies
inventory
• I2C communication interface
• 8kV ESD rating for serial lines
• Pb-free (RoHS compliant)
Applications
• Video entertainment systems
• Industrial computing terminals
• Remote cameras
3.3V
1.8V VDD_IO
3.3V
1.8V VDD_IO
16
VIDEO
SOURCE
RGBA/C
VSYNC
HSYNC
DATAEN
PCLK_IN
ISL34321
27nF 10m DIFFERENTIAL CABLE 27nF
SERIOP
SERIOP
27nF
SERION
27nF
SERION
REF_CLK
PCLK_IN
ISL34321
RGBA/C
VSYNC
HSYNC
DATAEN
PCLK_OUT
16
VIDEO
TARGET
VDD_IO
VDD_IO
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL34321
wwwE.DlaetcaStrhieceat4l US.pcoemcifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling
capacitor = 27nF. (Continued)
PARAMETER
I2C
I2C Clock Rate (on SCL)
I2C Clock Pulse Width (HI or LO)
I2C Clock Low to Data Out Valid
I2C Start/Stop Setup/Hold Time
I2C Data in Setup Time
I2C Data in Hold Time
I2C Data out Hold Time
SYMBOL
fI2C
CONDITIONS
MIN
TYP
MAX
UNITS
100 400 kHz
1.3 µs
0 1 µs
0.6 µs
100 ns
100 ns
100 ms
NOTES:
3. IDDIO is nominally 50µA and not included in this total as it is dominated by the loading of the parallel pins
4. This parameter is the output data skew from the invalid edge of PCLK_OUT. The setup and hold time provided to a system is dependent on the
PCLK frequency and is calculated as follows: 0.5 * fIN - tDV..
Pin Descriptions
DESCRIPTION
PIN NUMBER
47 to 40,
9 to 2
16
17
15
20
39
33, 32
18
19
24, 23
25, 26
27
12
10
28
PIN NAME
SERIALIZER
DESERIALIZER
RGBA[7:0], RGBC[7:0] Parallel video data LVCMOS inputs with
Hysteresis
Parallel video data LVCMOS outputs
HSYNC
Horizontal (line) Sync LVCMOS input with
Hysteresis
Horizontal (line) Sync LVCMOS output
VSYNC
Vertical (frame) Sync LVCMOS input with
Hysteresis
Vertical (frame) Sync LVCMOS output
DATAEN
Video Data Enable LVCMOS input with
Hysteresis
Video Data Enable LVCMOS output
PCLK_IN
Pixel clock LVCMOS input
PLL reference clock LVCMOS input
PCLK_OUT
Default; not used
Recovered clock LVCMOS output
SERIOP, SERION
High speed differential serial I/O
High speed differential serial I/O
VHSYNCPOL
CMOS input for HSYNC and VSYNC Polarity
1: HSYNC & VSYNC active low
0: HSYNC & VSYNC active high
VIDEO_TX
SDA, SCL (Note 5)
I2CA[1:0] (Note 5)
MASTER
CMOS input for video flow direction
1: video serializer
0: video deserializer
I2C Interface Pins (I2C DATA, I2C CLK)
I2C Device Address
I2C Master Mode
1: Master
0: Slave
RSTB/PDB
CMOS input for Reset and Power-down. For normal operation, this pin must be forced high. When
this pin is forced low, the device will be reset. If this pin stays low, the device will be in PD mode.
STATUS
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: otherwise
Note: serializer and deserializer switch roles during side-channel reverse traffic
REF_RES
Analog bias setting resistor connection; use 3.16kΩ ±1% to ground
5 FN6870.0
March 16, 2009
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