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PDF ISL34341 Data sheet ( Hoja de datos )
| Número de pieza | ISL34341 | |
| Descripción | WSVGA 24-Bit Long-Reach Video SERDES | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
December 15, 2008
ISL34341
FN6827.0
WSVGA 24-Bit Long-Reach Video
SERDES with Bi-directional Side-Channel
The ISL34341 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed
differential signal. This differential signal is converted back to
parallel video at the remote end by the deserializer. It also
transports auxiliary data bi-directionally over the same link
during the video vertical retrace interval.
I2C bus mastering allows the placement of external slave
devices on the remote side of the link. An I2C controller can
be placed on either side of the link allowing bi-directional I2C
communication through the link to the external devices on
the other side. Both chips can be fully configured from a
single controller or independently by local controllers.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL34341INZ* ISL34341INZ -40 to +85 64 Ld EPTQFP Q64.10x10C
*Add “-T13” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3.3V
1.8V VDD_IO
Features
• 24-bit RGB transport over single differential pair
• 6MHz to 40MHz pixel clock rates
• Bi-directional auxiliary data transport without extra
bandwidth and over the same differential pair
• I2C Bus Mastering to the remote side of the link with a
controller on either the serializer or deserializer
• 40MHz PCLK transports
- SVGA 800x600 @ 70fps, 16% blanking
- WSVGA 1024x600 @ 60fps, 8% blanking
• Internal 100Ω termination on high-speed serial lines
• DC balanced with industry standard 8b/10b line code
allows AC-coupling
- Provides immunity against ground shifts
• Hot plugging with automatic resynchronization every line
• 16 programmable settings each for transmitter amplitude
boost and pre-emphasis and receiver equalization allow
for longer cable lengths and higher data rates
• Programmable power-down of the transmitter and the
receiver
• Same device for serializer and deserializer simplifies
inventory
• I2C communication interface
• 8kV ESD rating for serial lines
• Pb-free (RoHS compliant)
Applications
• Navigation and display systems
• Video entertainment systems
• Industrial computing terminals
• Remote cameras
3.3V
1.8V VDD_IO
24
VIDEO
SOURCE
R G B A /B /C
VSYNC
HSYNC
DATAEN
PCLK_IN
ISL34341
27nF 10m DIFFERENTIAL CABLE
S E R IO P
SERION
27nF
27nF
S E R IO P
27nF
S E R IO N
REF_CLK
PCLK_IN
ISL34341
R G B A /B /C
VSYNC
HSYNC
DATAEN
PCLK_OUT
24
VIDEO
SINK
VDD_IO
VDD_IO
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL34341
www.EDaletacSthreiceat4lUS.cpoemcifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling
capacitor = 27nF. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
HS Generated Output Common Mode Voltage
HS Common Mode Serializer-Deserializer
Voltage Difference
VOCM
ΔVCM
2.35
20 120
HS Differential Output Impedance
HS Output Latency
HS Output Rise and Fall Times
HS Differential Skew
HS Output Random Jitter
HS Output Deterministic Jitter
HIGH SPEED RECEIVER
ROUT
tLPD
tR/tF
tSKEW
tRJ
tDJ
Part-to-part
20% to 80%
80 100 120
4 7 10
150
<10
13.4
40
HS Differential Input Voltage
HS Generated Input Common Mode Voltage
HS Differential Input Impedance
HS Maximum Jitter Tolerance
I2C
I2C Clock Rate (on SCL)
I2C Clock Pulse Width (HI or LO)
I2C Clock Low to Data Out Valid
I2C Start/Stop Setup/Hold Time
I2C Data in Setup Time
I2C Data in Hold Time
I2C Data out Hold Time
VID
VICM
RIN
fI2C
150
2.32
80 100 120
0.52
100 400
1.3
01
0.6
100
100
100
UNITS
V
mV
Ω
PCLK
ps
ps
psrms
psP-P
mVP-P
V
Ω
UIP-P
kHz
µs
µs
µs
ns
ns
ms
Pin Descriptions
PIN NUMBER
52 to 63,
2 to 13
22
23
21
26
51
41, 40
24
25
PIN NAME
SERIALIZER
RGBA[7:0],
Parallel video data LVCMOS inputs
RGBB[7:0], RGBC[7:0]
HSYNC
Horizontal (line) Sync LVCMOS input
VSYNC
Vertical (frame) Sync LVCMOS input
DATAEN
Video Data Enable LVCMOS input
PCLK_IN
Pixel clock LVCMOS input
PCLK_OUT
Default; not used
SERIOP, SERION
High speed differential serial I/O
HSYNCPOL
CMOS input for HSYNC
1: HSYNC is active low
0: HSYNC is active high
VSYNCPOL
CMOS input for VSYNC
1: VSYNC is active low
0: VSYNC is active high
DESCRIPTION
DESERIALIZER
Parallel video data LVCMOS outputs
Horizontal (line) Sync LVCMOS output
Vertical (frame) Sync LVCMOS output
Video Data Enable LVCMOS output
PLL reference clock LVCMOS input
Recovered clock LVCMOS output
High speed differential serial I/O
5 FN6827.0
December 15, 2008
5 Page 
ISL34341
www.TDahtaiSnhePetl4aUs.ctoimc Quad Flatpack Exposed Pad Plastic Packages (EPTQFP)
-A-
E E1
D
D1
-D-
EJECTOR PIN MARK
NOT PIN #1 ID
PIN 1
TOP VIEW
GAGE
PLANE
0o-7o
0.020
0.008
MIN
0o MIN
0.25
0.010
L
11o-13o
A2 A1
11o-13o
PIN 1
Q64.10x10C (JEDEC MS-026ACD-HU ISSUE D)
64 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED
PAD PACKAGE
MILLIMETERS
SYMBOL
MIN
MAX
NOTES
A - 1.20 -
A1 0.05 0.15
-
-B-
A2 0.95 1.05
-
b 0.16 0.28 6
b1 0.17 0.23
-
D
11.80
12.20
3
D1 9.90 10.10 4, 5
D2 2.90 3.10
-
e
E
11.80
12.20
3
E1 9.90 10.10 4, 5
E2 2.90 3.10
-
L 0.45 0.75 -
N 64 7
e 0.50 BSC -
NOTES:
Rev. 0 10/08
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
7. “N” is the number of terminal positions.
EJECTOR PIN MARK
NOT PIN #1 ID
E2
EJECTOR PIN MARK
NOT PIN #1 ID
D2
BOTTOM VIEW
-H-
SEATING
A PLANE
0.08
0.003
-C-
0.08
0.003
M
C
A-B S
DS
b
b1
0.09/0.16
0.004/0.006
BASE METAL
WITH PLATING 0.09/0.20
0.004/0.008
11 FN6827.0
December 15, 2008
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL34341.PDF ] | |
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